Hi, Petr,
I think the counter of COP module uses counting down mode, when counter reaches up to zero, the COP reset event happens. The timeout is dependent on COPT and COPCLKS bits in SIM_COPC register. If you set the COPT as 2b'11 and set COPCLKS as 1b'0, the COP uses 1KHz LPO clock, the period is (2**10)*1ms=1024ms.
You can use PIT to generate an interrupt, in the ISR, you can feed dog by writting 0x55 and 0xAA to SIM_SRVCOP, it is okay, the PIT period must be less than 1024ms.
Pls refer to section 12.2.17 COP Control Register (SIM_COPC) in reference manual of Kl16.
Hope it can help you
BR
Xiangjun Rong