Hi Tc an Phlip,
This is still incorrect, incomplete and unclear:
The following registers and bits are cleared by RSTD
• Data Port register
• Buffer is cleared and initialized.
• Present State register
• Buffer Read Enable
• Buffer Write Enable
• Read Transfer Active
• Write Transfer Active
• DATA Line Active
• Command Inhibit (DATA) Protocol Control register
• Continue Request
• Stop At Block Gap Request Interrupt Status register
• Buffer Read Ready
• Buffer Write Ready
• DMA Interrupt
• Block Gap Event
• Transfer Complete
There are 1) formatting errors, 2) ambiguous names, and 3) not all bit are cleared in all registers.
1) Formatting:
The following registers and bits are cleared by RSTD
• Data Port register
• Buffer is cleared and initialized.
• Present State register
• Buffer Read Enable
• Buffer Write Enable
• Read Transfer Active
• Write Transfer Active
• DATA Line Active
• Command Inhibit (DATA) MISSING NEW LINE Protocol Control register
• Continue Request
• Stop At Block Gap Request MISSING NEW LINE Interrupt Status register
• Buffer Read Ready
• Buffer Write Ready
• DMA Interrupt
• Block Gap Event
• Transfer Complete
2) Search the manual for each of the above names. You will be frustrated to only find them in ONLY the one table.
Using register names that result in unambiguous search results in the manual would be super helpful
like SDHC_SYSCTL or the full name and Buffer Data Port register or better yet SDHC_DATPORT
3) Not all the bits in all the registers are cleared. The test is simple: a) set all the non-reserved bits in SDHC_PROCTL b) assert SDHC_SYSCTL[RSTD] and c) read the results of SDHC_PROCTL.
The point I would like to reinforce, is that the documentation can only add value for the end user if it is an unambiguous reference.
If I had described the test above as: do the reset and read the register. Would that be clear? What reset? System reset POR on reset or SDHC_SYSCTL[RSTD]?
David
