System control register.
RSTD in the SYS CTRL register (PROCTL) - it’s not clearly documented that DTW bit gets cleared when this is asserted.
The following registers and bits are cleared by RSTD
• Data Port register
• Buffer is cleared and initialized.
• Present State register
• Buffer Read Enable
• Buffer Write Enable
• Read Transfer Active
• Write Transfer Active
• DATA Line Active
• Command Inhibit (DATA) Protocol Control register
• Continue Request
• Stop At Block Gap Request Interrupt Status register
• Buffer Read Ready
• Buffer Write Ready
• DMA Interrupt
• Block Gap Event
• Transfer Complete
Setting SYS_CTRL[RSTD] will clear all the registers mentioned in the RSTD field description. DTW field will be clear if set, DTW is considering as PROT_Command Inhibit (DATA) Protocol Control Registers.
The above is in reference to
K66 Sub-Family Reference Manual
Supports: MK66FN2M0VMD18, MK66FX1M0VMD18,
Document Number: K66P144M180SF5RMV2
Rev. 2, May 2015