Adding SRAM to a K60-based custom board

[MWMinor]

We are developing a custom board based on the MK60DN512VMD10 - although the architecture is very similar to the TWR K60 board.

The application is being developed within the MCUxpresso IDE and free RTOS. I have loaded and successfully run the lwip demo application although this uses nearly all the 128K RAM available on the on-chip RAM.

So we are adding some SRAM to the custom board and looking at the IS61WV102416BLL part.

There are some similar posts I have noticed that utilize this or similar parts but they have experienced some difficulties in doing this and getting reliable operation. Looking at the application note Using FlexBus Interface for Kinetis Microcontrollers it appears that the flexbus address lines FBA1 - A19 should be connected to the RAM A0 - A18 and that Flexbus FBA0 should drive the Upper Byte and Lower Byte control inputs to the SRAM - see diagram below.

Is this correct....? - or are the existing posts on this subject which seem to connect the flexbus FBA0-18 to SRAM A0-18 with the Upper Byte and Lower Byte selects driven by the byte enable outputs from the MCU correct. This is the way the project is currently configured, please see extract from project pin routing below..?

This is how the connections are currently configured but we are hesitant to progress to completing the pcb board layout as any changes to the above will have a big impact on the board layout.

[xiangjun_rong]

Hi,

I suppose that you referred to AN4393.pdf, obviously the hardware connection in the AN4393.pdf is correct, but the hardware connection can only access SRAM in BYTE(8 bits data bus) mode instead of half-word(16 bits data bus) mode although the external SRAM supports half-word access.

Of course, the FlexBUS of K60 supports half-word(16 bits data bus) access.

This is the signals of SRAM IS61WV102416BLL 

You can connect as following:

FB_A1~FB_A20 of FlexBus are connected to A0~A19

FB_D0~FB_D15 of FlexBus are connected to I/O0~I/O15

FB_BE_7_0 of FlexBus is connected to /LB

FB_BE_15_8 of FlexBus is connected to /UB

FB_OE of FlexBus is connected to /OE

FB_RW of FlexBus is connected to /WE

one of FB_CS[x] is connected to /CS

Furthermore, I suppose that you have to connect two 74ls374, with the FB_ALE edge, the FB_AD[15:0] are latched as FB_A[15:0], ply pay the edge of the flip-flop(rising/falling).

In this way, you can access the SRAM with byte or half-word width.

Hope it can help you

BR

XiangJun Rong

[MWMinor]

Hi thanks for the information.

The requirement to connect the A0 pin from the MCU to the A0 pin of the SRAM is understood as the SRAM is 16 bits wide.

As my pin-out for the MCU currently assigns A20 pin to be SPI2-CK, I cannot use this pin, but I believe we can reduce the SRAM from 2M Bytes to 1M Bytes so the SRAM we will use is the IS61WV51216BLL instead.

But I want to run the interface in non-multiplex mode to avoid the need to use the address latching signal.

I am also using BE31-24 for the UpperByte and BE23-16 for the LowerByte as I am connecting to FB_AD31 to FB_AD16 for data(so no byte lane shifting).

I have attached the current FB pin assignment - does this look correct..?

Thanks

[xiangjun_rong]

Hi,

I have checked your SRAM connection, you connect FB_D[31:16] as 16 bits data bus, I suppose it is okay.

Regarding A20 pin of SRAM, I suppose you can connect the pin to a GPIO, in this way, you can access all cell of SRAM.

Hope it can help you

BR

XiangJun Rong

[MWMinor]

With regard to the A20 pin, I didn't want to connect this to a general purpose IO pin, as I am hoping that once the SRAM is available to the MCU, it's usage will be the same as the on-chip RAM and that the application can use the extend RAM. If the A20 pin has to be driven by a GPIO pin, the surely the application needs to drive the RAM differently..??

Is this not the case..?

[xiangjun_rong]

Hi,

Okay, you can connect the A20 of SRAM to GND directly, in this way, only half of memory can be used, this is a drawback.

BR

XiangJun Rong

[MWMinor]

Thanks for getting back to me and agreed tying A20 of the SRAM to ground would work, but we have decided to use a device that's half the size (1M Byte instead of 2M Byte) is a more cost effective solution.

Regards

MWM

[MWMinor]

Sorry about that, the first sentence above should read...

"The requirement to connect the A1 pin from the MCU to the A0 pin of the SRAM........"