AN4533 Swap Problem - PFlashGetSwapStatus returns FTFx_ERR_MGSTAT0

[jmag99]

I get this error, sometimes I cannot recover without going back and programming with the JTAG debugger.  Does anyone know what causes it and what it actually checks to determine the error?  The reference manual has this:

Any errors have been encountered during the swap determination and

program-verify operations

But it's not enough information to tell me what is causing the error.  Are there registers that I can check to see what is going on?

[Kan_Li]

This return value is a result from calling FlashCommandSequence(), when bit0 of FTFL_FSTAT is set. Please kindly refer to the following for details.

I am not sure where you put the swap indicators, actually if the sectors containing swap indicators get erased in UPDATE or UPDATE-ERASED state, by some process to update the firmware or something like that, the swap system would report issue.

Hope that helps,

Have a great day,
Kan

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[jmag99]

One other question that I had.  I am supplying that address of 0x7F000 as the swap indicator area.  It appears that the actual swap indicator is not at that exact address, but really 12 bytes in from there.  Is there any description of how this swap indicator area is mapped out and where the data should be found?

[jmag99]

To narrow down the problem, I am trying to ensure that the swap field and swap indicators are correct.  I am using the following code to read the IFR Swap Field:

				returnCode = FlashReadResource(&ftflCfg, (PFLASH_BLOCK_BASE + PFLASH_IFR_OFFSET + 0), dataReadback, FlashCommandSequence);

which returns 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF

and

				returnCode = FlashReadResource(&ftflCfg, (PFLASH_BLOCK_BASE + PFLASH_IFR_OFFSET + 8), dataReadback, FlashCommandSequence);

which returns 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0D

I think the 0x00 0x00 from the first response is the swap enable field, meaning it's enabled.  I don't see any data in the swap indicator address though.  Also, how could the address fit into just 2 bytes (according to section 30.4.12.14.1 - Swap state determination)?

The specific processor is MK60FN1M0VLQ12 rev 3N96B.