Hello again,
I'm glad it is working. Sorry about the ACKISO issue.
So there really two different hold types 1) I/O hold that happens in STOP, VLPS, and LLS that release automatically and 2) I/O and OSC hold that only is released with the write to ACKISO.
Say you have the Oscillator and GPIO set up before going inteo VLLS1. Some of the GPIO are outputs driving low and the OSC is enabled to be running in the low power mode. After the wakeup event the MCU exits the low power mode through the reset flow if waking from VLLSx low power modes. The set up for the OSC and GPIO are lost with the reset, but until you write the ACKISO bit, the pins are held in state and the oscillator will continue to oscillate. The output will continue to be same output state at the pin while you are in the low power mode. Upon wakeup, in order not to glitch you I/O and stop your OSC for the short time between the ACKISO and re-initializing the I/O and OSC it is recommended to complete the I/O and module initialization and re-write the OSC registers in either the OSC block or MCG prior to writing the ACKISO bit. For the output driving low, you would re-run the setup code that initialized the GPIO, initialize the UART or timer output, or other peripherals that can control or be sensitive to pins prior to the write to ACKISO.
By the way, ACKISO, or the hold of pin state, is a feature that has been available for many years on Freescale MCU's including the S08 and CFV1 devices.
Best Regards,