ADC trigger via FTM2 doesn't work

cancel
Showing results for 
Search instead for 
Did you mean: 

ADC trigger via FTM2 doesn't work

Jump to solution
599 Views
robertogiovinet
Contributor III

Hello everybody

I'm using MKE04Z128VLH4 MCU, and I've some problems: I'm using ADHWT trigger source with FTM2 init trigger (0b010). I configured channels CH0 e CH1 of FTM2 in combined Mode, and I used FTM0 as Trigger1 for PWM synchronization. In the register FTM2_EXTTRIG I've setted INITTRIGEN bit, so I excpeted that every period of FTM2 there's an ADC interrupt, but there's NOT!

I've tried to change ADHWT to FTM2 matching, and I've changed bits in the FTM2_EXTTRIG register, but there's no solution: it doesn't work.

PWM signals are OK, but I can't synchronize ADC conversion with FTM2 timer and I don't know why.

Here's FTM2 initialization.

As you can see I use only channel 0 and channel 1.

void FTM2_Init(void)
{
/* Fault control disabled for all channels ,
write protection disabled, FTM enabled */
FTM2_MODE = FTM_MODE_FAULTM(0b00) | FTM_MODE_WPDIS_MASK | FTM_MODE_FTMEN_MASK;

/* FTM functional in debug mode */
FTM2_CONF = FTM_CONF_BDMMODE(0b11);

/* Initial value of the FTM counter */
FTM2_CNTIN = 0x00000000;
/* Modulo value of the FTM counter set according to PWM_MODULO macro
value */
FTM2_MOD = (PWM_PERIOD << 2) - 1;

/* High-true pulses (set on channel (n) match, clear on channel (n+1)
match) */
FTM2_C0SC = FTM_CnSC_ELSB_MASK;
FTM2_C1SC = FTM_CnSC_ELSB_MASK;
//FTM2_C2SC = FTM_CnSC_ELSB_MASK;
//FTM2_C3SC = FTM_CnSC_ELSB_MASK;
//FTM2_C4SC = FTM_CnSC_ELSB_MASK;
//FTM2_C5SC = FTM_CnSC_ELSB_MASK;

/* Trigger 1 enabled, OUTMASK register is updated by the PWM synchronization,
the maximum loading point is enabled */
FTM2_SYNC = FTM_SYNC_TRIG1_MASK | FTM_SYNC_SYNCHOM_MASK | FTM_SYNC_CNTMAX_MASK;

/* Fault disabled, PWM synchronization enabled, dead time insertion enabled,
combine feature enabled, and complementary mode enabled for all channel
pairs */
FTM2_COMBINE |= FTM_COMBINE_COMBINE0_MASK | FTM_COMBINE_COMP0_MASK | FTM_COMBINE_DTEN0_MASK | FTM_COMBINE_SYNCEN0_MASK; // Abilito il Combine, Complementarità e dead time per coppia canali 0-1
//FTM2_COMBINE |= FTM_COMBINE_COMBINE1_MASK | FTM_COMBINE_COMP1_MASK | FTM_COMBINE_DTEN1_MASK | FTM_COMBINE_SYNCEN1_MASK; // Abilito il Combine, Complementarità e dead time per coppia canali 2-3
//FTM2_COMBINE |= FTM_COMBINE_COMBINE2_MASK | FTM_COMBINE_COMP2_MASK | FTM_COMBINE_DTEN2_MASK | FTM_COMBINE_SYNCEN2_MASK; // Abilito il Combine, Complementarità e dead time per coppia canali 4-5


/* Dead time prescaler 1 (system clock div. by 1), dead time value set
according to PWM_DEADTIME macro value */
FTM2_DEADTIME = FTM_DEADTIME_DTPS(0b00) + FTM_DEADTIME_DTVAL(0b000001); //Il bus clock alimenta FTM2 (24MHz). 0x0A -> 400ns deadtime

/* Initialization trigger enabled */
FTM2_EXTTRIG = FTM_EXTTRIG_INITTRIGEN_MASK;
//FTM2_EXTTRIG = FTM_EXTTRIG_CH0TRIG_MASK;

/* Even (high-side) channels active low, odd (low-side) channels active
high */
//FTM2_POL = FTM_POL_POL4_MASK | FTM_POL_POL2_MASK | FTM_POL_POL0_MASK;

/* HW trigger activates SWOCTRL, OUTMASK register synchronization,
and FTM counter synchronization; software trigger activates SWOCTRL,
OUTMASK, MOD, CNTIN, CV register synchronization; enhanced PWM
synchronization mode selected; SWOCTRL register is updated by the PWM
synchronization; FTM does not clear the TRIG1 bit when HW trigger 1 is
detected */

FTM2_SYNCONF |= FTM_SYNCONF_SYNCMODE_MASK; //Enhanced PWM synchronization is selected
FTM2_SYNCONF |= FTM_SYNCONF_SWWRBUF_MASK; //The software trigger activates MOD, CNTIN, and CV registers synchronization
FTM2_SYNCONF |= FTM_SYNCONF_HWRSTCNT_MASK; //A hardware trigger activates the FTM counter synchronization
FTM2_SYNCONF |= FTM_SYNCONF_HWSOC_MASK; //A hardware trigger activates the SWOCTRL register synchronization
FTM2_SYNCONF |= FTM_SYNCONF_HWOM_MASK; //A hardware trigger activates the OUTMASK register synchronization
FTM2_SYNCONF |= FTM_SYNCONF_HWTRIGMODE_MASK; //FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
FTM2_SYNCONF |= FTM_SYNCONF_SWSOC_MASK; //The software trigger activates the SWOCTRL register synchronization
FTM2_SYNCONF |= FTM_SYNCONF_SWOM_MASK; //The software trigger activates the OUTMASK register synchronization
FTM2_SYNCONF |= FTM_SYNCONF_SWOC_MASK; //SWOCTRL register is updated with its buffer value by the PWM synchronization


/* All channels masked (forced to inactive state) */
//FTM2_OUTMASK = FTM_OUTMASK_CH5OM_MASK | FTM_OUTMASK_CH4OM_MASK | FTM_OUTMASK_CH3OM_MASK | FTM_OUTMASK_CH2OM_MASK | FTM_OUTMASK_CH1OM_MASK | FTM_OUTMASK_CH0OM_MASK;

/* Fault input filter disabled, fault inputs 1 */
//FTM2_FLTPOL = FTM_FLTPOL_FLT1POL_MASK ; //Uno 0 sull'input genera il Fault
Attesa_mul_2us(50);
//FTM2_FLTCTRL = FTM_FLTCTRL_FAULT1EN_MASK ;
//FTM2_FMS = 0x00000000; //Eventuali Fault Flags puliti...

/* Update of FTM settings */
FTM2_CNT = 1;

/* System clock div. by 1 selected as FTM source clock */
FTM2_SC = FTM_SC_CLKS(1) | FTM_SC_PS(0);

/* Set zero duty cycle */
FTM2_C0V = 0x0000;
FTM2_C1V = 0x0000;
//FTM2_C2V = 0x0000;
//FTM2_C3V = 0x0000;
//FTM2_C4V = 0x0000;
//FTM2_C5V = 0x0000;

/* Update OUTMASK, SWOCTRL, and CV by software trigger */
FTM2_SYNC |= FTM_SYNC_SWSYNC_MASK;

/* Enable loading of the CV registers with their buffered values */
FTM2_PWMLOAD |= FTM_PWMLOAD_LDOK_MASK;

During MCU initialization (before FTM2_INIT function):

SIM_SOPT0 |= SIM_SOPT0_ADHWT(0b010); //FTM2 init trigger ADC conversion

In the main program I wrote:

FTM0_CNT = 0;
FTM2_CNT = 0;
FTM2_C1V = 0x20;
FTM2_SYNC |= FTM_SYNC_SWSYNC_MASK; //SW updates
FTM2_PWMLOAD |= FTM_PWMLOAD_LDOK_MASK;

After this instructions I can see output on CH0 e CH1 pins of FTM2, but there's no ADC interrupt generation.

I've tried to change ADHWT to 0b011 value (FTM2 matching) and to change EXTTRIG register of FTM2, but I can't obtain what I want.

Any idea?

Thank you very much.

Roberto

Labels (2)
0 Kudos
1 Solution
194 Views
robertogiovinet
Contributor III

Hello everybody

I found what was the matter

In the ADC settings I've used FIFO mode, so I've forgot to set HTRGMASKE bit in ADC_SC5 and HTRGME bit in ADC_SC4. I don't know why I made a mistake like this.

In this way it works!

Thank you!

View solution in original post

0 Kudos
1 Reply
195 Views
robertogiovinet
Contributor III

Hello everybody

I found what was the matter

In the ADC settings I've used FIFO mode, so I've forgot to set HTRGMASKE bit in ADC_SC5 and HTRGME bit in ADC_SC4. I don't know why I made a mistake like this.

In this way it works!

Thank you!

View solution in original post

0 Kudos