ADC read affected by previous channel read

[nathan55421]

Hi everyone,

I am working on a MKL16Z256 MCU and I have a problem concerning ADC reads.

I am developping using the NXP SDK 2.2.0.

My program is split into two section :

1. Repeated, single channel ADC reads : I read one ADC channel (ADC0_CH13) connected to a potentiometer (without changing it).
2. Sequential ADC reads : I read 5 different channels (CH12, CH13, CH14, CH2 and CH1 : all connected to potentiometers) with a 100ms delay between each one.

The two sections of the program are executed in a loop (4s for section 1, then one complete round (~500ms) for section 2).

All ADC reads are started through software trigger and values are received via interrupts. 

When executing section 1, I have approximately the same ADC value (+/- 1 unit in 12 bits resolution). As the potentiometer is not touched, that's the expected behavior.

When executing section 2, I can see that the channel I have read in the first sequence (CH13), is giving me a value different from the one retrieved in section 1. The value seems to be affected by the voltage of the previous channel read. e.g : If CH12 is at 0, the value of CH13 in section 2 can be lower by about 10 units than the value read in section 1.

The difference obtained between section 1 and section 2 of the same channel also depends of the value itself. Here are the results of values in section 1 and 2 for different positions of the potentiometer (not changing it between sections, only after some time for filling next line).

ADC value in first section (repeated read of same channel)	ADC value in second section (inside sequence of all channels)	Difference
0	0	0
1558	1557	-1
2170	2164	-6
2245	2238	-7
2867	2856	-11
3077	3068	-9
3612	3605	-7
4095	4095	0

Would anyone have an idea about where the origin of the problem is or how to investigate further ?

Regards

Nathan

[xiangjun_rong · Accepted solution]

Hi,

First of all, i do not think there is huge difference between two samples if you convert the same DC channel, the maximum difference is 11 unit.

I think that the phenomenon may be interpreted by the Sample/Hold(S/H) device, when the capability of  external analog driving circuit is not enough, which will lead to the fact that the previous channel take effect on the S/H, because the S/H capacitor can not charge enough.

Pls try to adjust from hardware and software.

pls set the ADLSMP bit in the ADCx_CFG1 register to enlarge the sample time. what is the resistor of the potentiometer ? how about using a small potentiometer?

this is only my guess for the cause of the ADC sample difference.

BR

Xiangjun Rong

[nathan55421]

Hi Xiangjun,

On our PCB we are using 100K Ohm potentiometer. According to the reference manual and the application note I have found on the NXP website, that is an order of magnitude bigger than the internal resistor of the S/H device.

Following your advice, I have first tried to increase the sampling time through the ADLSMP and ADLSTS bits to have an additional 24 cycles. With this change, I end up with a maximum difference of 4 units instead of 11, which is already a better fit.

In a second time, I have tried changing the potentiometers for 10K ones. Even with a short sample time (cleared ADLSMP bit, the difference between section 1 and section 2 on this specific potentiometer is now negligeable (+/- 2 units), though we still see the impact of the previous channel read (-1 or 2 if previous channel is at 0, +1 or 2 when previous channel is at 4095). With a longer sampling time, the effect of the previous channel read is completely gone : no longer a difference with the position of the previous channel, only standard noise of one unit between two reads wich are to be expected from analog conversions.

Thank you very much for your answer.