ADC Speed

[lothar]

Hi there

I' m using a tower modul with a K20 72MHz MCU and i would like to use the ADC.

I've got the following questions:

CFG2[ADHSC] is used to configure a higher clock input frequency. This will allow

faster overall conversion times. To meet internal ADC timing requirements,

CFG2[ADHSC] adds additional ADCK cycles. Conversions with CFG2[ADHSC]=1 take

two more ADCK cycles. CFG2[ADHSC] must be used when the ADCLK exceeds the

limit for CFG2[ADHSC]=0.

From which ADCK upwards it must be set? I didnt found that in the manual

After a reset what is the normal clock speed of everything?

Something like that:

Option 2:

Clock Frequency

Core clock 72 MHz

System clock 72 MHz

Bus clock 36 MHz

FlexBus clock 36 MHz

Flash clock 24 MHz

Am I right with that? Thanks in advance for your answer.

best regards

Lothar

[apanecatl · Accepted solution]

Hi Lothar

After a POR, all the mcu modules will be clocked at a 20.1 MHz frequency, which is predetermined, once the mcu initializes your code it will set up the modules to the CLK frequency you configured.

Regarding ADCK, it has two ranges:

≤ 13 bit modes    1 MHz < ADCK < 18 MHz

16 bit modes       2 MHz < ADCK < 12 MHz

Depending which resolution you use it is the ADCK range you can work with.

[lothar]

Thanks for your answer

In my case the clock is somehow set without doing anything. I guess there is a function start() which is called by default and it sets the OUTDIV1-4 Registers and some other stuff. It makes it like that:

Core clock 72 MHz          OUTDIV1 = 0

System clock 72 MHz      OUTDIV1 = 0

Bus clock 36 MHz            OUTDIV2 = 1

FlexBus clock 36 MHz      OUTDIV3 = 1

Flash clock 24 MHz          OUTDIV4 = 2

The second information about the ADCK is very useful. But where have you found that?

I searched in the Datasheet and in Cookbook for SAR ADC Measurements.