ADC Differential Mode

[ZYXEmbedded]

Hi,

I enabled differential mode by setting enableDifferentialPair to true (CADC driver), and I get values between 0 and 4095.

2048  when ADC channel 0 = ADC channel 1

0 < ADC result < 2048 (when ADC channel 0 < ADC channel 1)

2048 < ADC result < 4095 (when ADC channel 0 > ADC channel 1).

 I was expecting the values to be between -4095 and 4095 (signed). The ADC result is 16 bit (3 bits left shifted and the 16th bit is signed bit when using differential mode).

Is there an example code for configuring differential mode?

I'm using MKV46 .

[D4Worker]

Hi there, I am also using the same series. 
 
I guess the ADC register result, ADC->RSLT[0], is not producing something in the negative range. 
What I did is making a conversion function/statement to the unit / range I want. 

For your case, you are mapping (ch1-ch0) to -4095 ~ +4095 whilst the original result It 0-4095
What about a quick fix 

signed count_you_finally_get  = ((Result_original >> 3 ) << 1 ) -  4095 ?

Here >> 3 is making it right align. 
<<1 is x2 for mapping your wished range for 8192 counts. 
-4095 is the offset 

I expect there are some register setting can help manipulate the result format but I try to prevent diving into it. = )

[ZYXEmbedded]

Thank you @D4Worker,

I did something similar.

Right now I'm setting an offset of 2048, so the result is between -2048 and 2048. And then I left-shift the 13-bit result by one. I was hoping there was a way to get the values between -4095 and 4095 without performing additional operations.

[jingpan]

Hi @ZYXEmbedded ,

This is a 12bit ADC. If the output is from -4096~+4096, that is 13bit. The signal bit is also a bit.

In fact, Differential measurements return the max value ((2**12)-1) when the + input is V REFH and the - input is VREFLO , return 0 when the + input is at V REFLO and the - input is at VREFH , and scale linearly between based on the voltage difference between the two signals.

Regards,

Jing