ADC Clock

[dsherman]

I'm a little puzzled on one thing about the ADC clock.  According to the KE06 data sheet, the conversion clock has to be between 0.4 and 8 MHz for high speed mode.  If I'm using a 24 MHz bus clock, then I must use bus clock/2 as the source, and divide that by 2 to get to 6 MHz.  What if I divide that by 4 to get 3 MHz?  Does it just mean that conversions take longer?

[daweiyou]

Hi:

Yes, normally slower ADC clock will take longer time to finish conversions.

24.4.4.5 Sample time and total conversion time

The total conversion time depends on the sample time (as determined by

ADC_SC3[ADLSMP]), the MCU bus frequency, the conversion mode (8-bit, 10-bit or

12-bit), and the frequency of the conversion clock (fADCK).

Dawei You（尤大为）

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