Introduction The NAFEB43388 is a highly configurable, industrial-grade, 8-input universal analog front-end designed for high-precision measurement applications such as PLCs, DCS I/O modules, remote/distributed I/O, data acquisition systems, instrumentation, and industrial automation. It integrates a 24-bit sigma-delta ADC, 13-bit DAC, high-voltage multiplexers, programmable gain amplifiers, precision references, diagnostics, and an integrated sense resistor with protection switch for current measurements. The NAFEBx3388-EVB evaluation board supports evaluation of pin-compatible NAFEB43388/NAFEB73388 family devices and is intended to demonstrate high-precision industrial measurements using the FRDM-MCXN947 MCU platform and a Windows-based GUI. For detailed register settings, timing diagrams, electrical limits, and calibration procedures, please refer to the latest NAFEB43388 product data sheet and the NAFEBx3388-EVB user manual available on nxp.com.  1. What is the NAFEB43388? The NAFEB43388 is a highly configurable multichannel universal-input Analog Front-End intended for precision industrial measurements. It integrates a 24-bit sigma-delta ADC, 13-bit DAC, low-leakage high-voltage multiplexers, low-offset and low-drift PGA stages, internal voltage references, diagnostics, and an integrated current-sense resistor protected by a smart e-fuse circuit. 2. What applications is the NAFEB43388 designed for? Typical applications include PLC and DCS I/O modules, remote and distributed I/O modules, sensor and data acquisition systems, instrumentation, and industrial automation or process-control equipment. 3. How many analog inputs does the NAFEB43388 support? The device provides eight high-voltage analog inputs plus one common input. These inputs can be configured for single-ended, differential, or pseudo-differential measurements depending on the measurement topology and register configuration. 4. What types of signals can the NAFEB43388 measure? The NAFEB43388 supports software-configurable measurement of voltage, current, resistance, RTD, and thermocouple-type sensor signals. The supported input ranges include voltage up to ±12.5 V, current up to ±25 mA, and resistance measurement capability from 1 mΩ to 1 MΩ according to the fact sheet, while the datasheet describes programmable current excitation for resistance and RTD measurements. 5. What is the ADC resolution and data-rate range? The NAFEB43388 integrates a 24-bit sigma-delta ADC. For the low-power NAFEB43388 variant, the ADC data rate is configurable from 7.5 samples per second up to 288k samples per second, depending on the selected data-rate code, SINC filter configuration, and settling mode. 6. What is the DAC resolution and output capability? The integrated DAC has 13-bit resolution and can be configured for voltage output or current output. The DAC supports voltage output up to approximately ±12.5 V full-scale and current output up to approximately ±2.5 mA full-scale, with a DAC data rate up to 100 ksps. 7. What is the difference between NAFEB43388, NAFEB43188, NAFEB73388, and NAFEH73388? The NAFE family includes low-power and high-speed variants, with or without factory calibration and HART modem support. The NAFEB43388 is a low-power, 24-bit, 8-input device with factory calibration and no HART modem. The NAFEB43188 is similar but without factory calibration. The NAFEB73388 is a high-speed 24-bit, 8-input variant with factory calibration, and the NAFEH73388 adds HART modem support. 8. What is the NAFEBx3388-EVB? The NAFEBx3388-EVB is an evaluation board designed to evaluate pin-compatible NAFEB43388 and NAFEB73388 AFE devices. It enables high-precision industrial measurements using the FRDM-MCXN947 MCU platform and includes a GUI for configuring and testing the device. 9. What hardware is included in the NAFEBx3388 evaluation kit? The evaluation kit includes the NAFEBx3388 evaluation board, an FRDM-MCX947 evaluation board with custom firmware, and a USB cable. The EVB is connected to the FRDM-MCX947 board through Arduino-compatible connectors. 10. How is the NAFEBx3388-EVB powered? The EVB can be powered using the supplied 24 V AC-DC adapter connected to J307, with jumpers J308, J309, and J310 set to the 2-3 position. Alternatively, external supplies can be applied: AVDD/DVDD = 3.75 V on J300, HVDD = +15.4 V on J301, and HVSS = -15.4 V on J302, accounting for the voltage drop across the protection diode in the supply path. 11. How does the NAFEB43388 support voltage measurements? The AFE can measure differential, pseudo-differential, and single-ended voltage signals. Single-ended measurements are performed by connecting the positive signal to AIxP or AIxN and the negative signal to AICOM, while differential measurements use the corresponding AIxP and AIxN pair. 12. What voltage input ranges are available? The input range depends on the total programmed channel gain. For single-ended input, the nominal linear ranges include ±10 V at gain 1, ±5 V at gain 2, ±2.5 V at gain 4, ±0.625 V at gain 16, ±0.313 V at gain 32, and ±0.156 V at gain 64. For differential input, the corresponding nominal linear ranges are ±20 V, ±10 V, ±5 V, ±1.25 V, ±0.625 V, and ±0.313 V. 13. How does the NAFEB43388 support current input measurements? The AI1P pin can measure current using the integrated 25 Ω sense resistor and the configurable current-input protection switch, CISW. This supports common industrial current ranges such as ±20 mA, 0 mA to 20 mA, and 4 mA to 20 mA. 14. What protection is available for current input mode? When current input mode is selected on AI1P, the integrated CISW protection switch supports fault handling. The datasheet describes three current levels: approximately 50 mA short-circuit or overcurrent threshold, 30 mA overload threshold, and 12 mA current-limiter level. The overcurrent deglitch time, overcurrent limit time, and limiter delay can be configured. 15. What is the purpose of the programmable gain amplifiers? The NAFEB43388 includes two PGA stages. PGA1 operates in the high-voltage domain and supports gains of 1 and 16, while PGA2 operates in the low-voltage domain and supports gains of 1, 2, and 4. Combining both stages provides total gains from 1 to 64, allowing the input range to be matched to the signal amplitude. 16. What are the available ADC reading modes? The NAFEB43388 supports five conversion modes: Single-Channel Single-Reading, Single-Channel Continuous-Reading, Multichannel Single-Reading, Multichannel Multireading, and Multichannel Continuous-Reading. These modes allow the host to choose between one-shot, continuous, host-driven, semi-autonomous, or autonomous multichannel acquisition. 17. When should normal settling or single-cycle settling be used? Normal settling is better suited for single-channel reading where maximum data rate is preferred, while single-cycle settling is recommended for multichannel systems to avoid settling-time error after switching channels. In normal settling, the ADC output stabilizes after four samples, while in single-cycle settling the output is stable in one cycle, but the effective data rate is four times slower. 18. What factors affect noise performance? Noise performance depends mainly on the selected data rate, PGA gain, digital filter order, and settling mode. Lowering the data rate reduces the equivalent noise bandwidth and therefore reduces noise. Increasing PGA gain can reduce input-referred noise because the PGA contributes less noise than the ADC. Higher-order digital filtering can also reduce noise by narrowing the effective bandwidth. 19. What calibration options are available? The NAFEB43388 includes user-accessible calibration coefficient registers for analog input gain, analog input offset, extra calibration coefficients, and DAC output calibration. Factory-calibrated options load coefficients from nonvolatile memory during power-up or reset, and users can also perform application-specific calibration using the available registers and GUI procedures. 20. What accuracy can be achieved with calibration? For voltage input with user calibration, the datasheet specifies typical room-temperature TUE of 0.002 %FS and maximum ±0.005 %FS under the stated conditions. Across temperature, typical TUE is listed as 0.05 %FS with maximum ±0.1 %FS. For current input using the internal sense resistor and user calibration, the listed typical room-temperature TUE is 0.00125 %FS with maximum ±0.005 %FS. 21. How is an external 4-wire PT100 connected and measured? For the external 4-wire PT100 demo, one red RTD wire is connected to AI2P and one white wire to AI3P to provide the current forcing path, while the other red and white wires are connected to AI3N and AICM for differential voltage sensing. The default GUI configuration uses AI3P-AI3N as the measured input, -2 mA DAC current excitation on AI2P, normal settling, PGA1 = 16x, PGA2 = 4x, 200 SPS, and SINC4_4 filtering. 22. What diagnostics are integrated in the NAFEB43388? The NAFEB43388 includes advanced diagnostics for fault and anomaly detection, including power-supply monitoring, under-/over-range detection on the signal path, redundant voltage-reference monitoring, temperature monitoring, CRC error detection, global alarm functionality, clock-deviation detection, and input/output overcurrent-related status flags. 23. How can multiple NAFEB43388 devices be synchronized? The device supports synchronization through the SYNCADC pin. A host-generated SYNC pulse can be connected to multiple NAFE devices so that conversions start simultaneously on the rising edge of the SYNCADC pulse. The device can also synchronize to the host using SYNCADC, synchronize the host to the NAFE data rate using DRDY, or share an external 18.432 MHz clock with the host for coherent measurements.

I²C communication is widely used due to its simplicity, but when the system grows (more devices, longer traces, different voltage domains), communication issues may appear. One common root cause is the incorrect use of I²C buffers or level translators. This post explains: How I²C logic levels really work Why buffers are needed Types of I²C Buffer Technologies How Static Voltage Offset (SVO) works Common design mistakes to avoid How I²C logic levels really work I²C does not use fixed voltages like 0 V or 5 V to define logic states. Instead, it uses thresholds relative to VCC: Logic 0 (LOW): below ~30% of VCC Logic 1 (HIGH): above ~70% of VCC Undefined region: between 30%–70% → signal is unreliable In real systems, signal levels may not behave ideally. Due to: Different driver strengths Load variations Buffer offset behavior You may observe three voltage levels, even though the protocol only defines two logic states. This can lead to misinterpretation of signals. We will explore this behavior in more detail in the following sections, especially when analyzing how I²C buffers and offset mechanisms work. Why buffers are needed You should consider an I²C buffer when: Bus capacitance exceeds ~400 pF Long PCB traces or cables are used Multiple devices are connected Different voltage domains are required Isolation between sections is needed Buffers divide the system into smaller segments and improve signal integrity. For a deeper understanding, refer to the training: The Ins and Outs of I²C Bus Buffers Types of I²C Buffer Technologies Different buffer architectures solve these challenges in different ways: Static Offset: Introduces a fixed voltage offset on one side of the bus, enabling direction detection. Incremental Offset: Adds a small dynamic voltage shift (~100 mV), allowing symmetrical bidirectional operation. Amplifier: Boosts sink current instead of shifting voltage, helping weak drivers control heavier loads. In this post, we will focus specifically on Static Offset buffers, as they are widely used and often misunderstood in system design. Static Offset Buffer Characteristics Static Offset buffers are commonly used due to their robust behavior: Fully bidirectional and support multi-master operation, including clock stretching and do not generate any ‘glitches’. Isolate bus segments electrically, preventing capacitance and loading on one side from affecting the other side. Each side operates independently with its own rise time and pull-up network. Regenerate signals, producing clean LOW levels independent of the input LOW amplitude. Use a fixed Static Voltage Offset (SVO), creating a slightly higher LOW level on one side of the buffer. This offset allows the buffer to determine the origin of a LOW signal and prevents latching. Weaknesses of Static Offset Buffers Require specific design rules due to their special offset voltage levels. Static Offset ports cannot be connected together on the same bus segment. Only one offset port should exist per bus segment. Add propagation delay, which must be considered in timing analysis. Multiple buffers can reduce the maximum achievable I²C bus speed The main challenge in I²C buffers is that the bus is bidirectional. Both master and slave can pull the line LOW. By introducing a fixed voltage offset, the buffer can distinguish which side initiated the LOW condition and correctly propagate the signal across the bus. How Static Voltage Offset (SVO) works Static Voltage Offset introduces an intentional voltage offset, so a LOW level is not always represented by 0 V. Instead, the buffer creates two valid LOW levels, both within the I²C specification. To achieve this, the input and output logic levels on the special side of the buffer are intentionally designed to be different.   The key concept is that the special output LOW voltage (VOL) is set slightly higher than the corresponding input HIGH threshold (VIH): For example: Special output VOL ≈ 0.7 V Special input VIH ≈ 0.55 V When the buffer drives the special side LOW at approximately 0.7 V, that voltage is still considered a valid LOW by other I²C devices on the bus. However, for the buffer's own special input, 0.7 V is interpreted as a HIGH because it is above its VIH threshold. As a result, the buffer's output cannot feed back into its own input, preventing the latching condition commonly found in simple bidirectional buffers. This enables the buffer to distinguish between two conditions: State 1: The voltage is between the special input threshold (VIL) and the offset level (VOL/SVO). This indicates that the LOW originated from one side of the buffer. State 2: The voltage is pulled much closer to 0 V, below the special threshold. This indicates that the LOW originated from the opposite side of the buffer. By monitoring these voltage levels, the buffer can determine where the LOW signal originated (Side A or Side B). Once the direction is identified, the buffer can correctly propagate the signal to the other side while avoiding feedback, latching, and communication conflicts. But, How Does the Buffer Determine the Signal Direction? The Buffer uses an internal voltage offset to automatically determine the direction of I²C signal propagation. The offset appears on the opposite side of the device that is actively pulling the bus LOW, allowing the buffer to identify the signal source and maintain proper bidirectional operation. The buffer continuously monitors the voltage present on both sides and compares it against the internal offset thresholds. Case 1: LOW originated from the Non-Offset side (A → B) A device on Side A pulls the line LOW. The buffer propagates this LOW to Side B while adding the static offset: Side A = LOW Side B = LOW + Offset As a result: Input = LOW Output = OFFSET The presence of the offset voltage indicates that the signal originated from the Non-Offset side and is being propagated toward the Offset side.   Case 2: LOW originated from the Offset side (B → A) A device on Side B pulls the line LOW. The buffer recognizes that the voltage has been driven below the offset threshold and propagates a true LOW toward Side A: Side B ≈ LOW Side A ≈ LOW As a result: Input = LOW Output = LOW The absence of an offset on the output indicates that the signal originated from the Offset side and is being propagated toward the Non-Offset side.   INPUT OUTPUT DIRECTION LOW LOW B SIDE TO A SIDE LOW OFFSET A SIDE TO B SIDE   Common design mistakes to avoid When using I²C buffers that implement Static Voltage Offset (SVO), it is important to carefully consider both device selection and system-level design. This is because not all buffers use the same offset value. Typically, the SVO can vary between approximately 0.1 V and 0.6 V, depending on the internal design of each device. This variation directly affects how LOW levels are interpreted and how signals are propagated between segments of the bus, which can ultimately impact the reliability of bidirectional communication. Another important aspect is that the offset is not always located on the same side of the buffer. In some devices, the offset is applied on Side B, while in others it is on Side A. There are even cases where the offset may dynamically change sides depending on the operating conditions. For this reason, it is essential to fully understand the internal behavior of the selected buffer in order to avoid unexpected system behavior. The easiest way to verify this is by reviewing the device datasheet and identifying whether it specifies a parameter such as the VOL–VILC difference, which represents the difference between the LOW-level output voltage and the LOW-level input voltage during a contention condition. Voltage contention occurs when both sides of the buffer attempt to pull the line LOW at the same time but with different voltage levels or drive strengths. Due to this variability, there is a very important design rule: SVO-based buffers must never be directly connected to each other, whether in series or in parallel. This means that you should not connect two buffer sides that both introduce a voltage offset, as their LOW levels will not align correctly. The reason for this limitation is that it can lead to errors in LOW-level propagation. In such cases, a LOW signal may propagate correctly in one direction but fail in the opposite direction, breaking the bidirectional behavior of the I²C bus, which is essential for proper communication.   These diagrams show correct implementations of SVO-based I²C buffers. In these configurations, only one side of the system introduces a static voltage offset, allowing the buffer to properly distinguish the origin of the LOW signal. This ensures correct bidirectional communication, stable signal propagation, and prevents contention or oscillation issues.         These diagrams illustrate incorrect configurations where two SVO-based buffers are directly connected. In this case, both sides introduce different LOW offset levels, preventing proper alignment of logic thresholds. As a result, the buffer may fail to correctly detect the signal origin, leading to incomplete LOW propagation, loss of bidirectional behavior, and potential communication failures.    

@SavinoLupo  MC33772C hello Savino, our customer have below SM relation questions, please help check. 1. For the diag_time and recv_time of SM_01, SM_02, SM_36, it didn’t specify how they are calculated. We tried to use the formula in the safety manual, but we can’t get the same result as that in the xlsx tool. If you use different formula, or there are other coefficient contributed to the result ? 2. Regarding to diag_time of SM_36, in the safety manual, it states that it is dependent on the VISENSE_OL, Imax and IISENSE_OL，but in the xlsx tool, during calculation, it didn’t include all of these parameters, why ? 3. Regarding to diag_time of SM_36, in the safety manual, it’s specified to take 32ms, but in the xlsx tool, it’s specified to take 64ms, what’s the reason ?