PCA2131: AF (Alarm Flag) in Control Register 2 will not be able to clear

[vikasgupta]

Hi everyone,

I am currently integrating the PCA2131 Automotive RTC into a Battery Management System (BMS).

I am encountering a persistent issue where the Alarm Flag (AF, bit 4 of Control_2 register 01h) is stuck high. Basic SPI communication is functioning perfectly-I can successfully set and read the time registers without issue. However, I cannot clear the AF flag during initialization.

Important Context:

• I have already ensured that all Alarm Enable (AE_X) bits in the alarm registers (0Ah through 0Eh) are set to 1 (disabled) prior to attempting to clear the AF flag.

The sequence I am executing:

1. Read Control_2 (Register 01h). The AF bit reads as 1.

2. Clear the flag by setting AF = 0 and AIE = 0 in my local struct.

3. Write the modified byte back to Control_2.

4. Read Control_2 again. The AF bit is still 1.

I have attached screenshots from my debug session showing the register states before clearing, during the clear operation, and after reading it back.

My Questions:

1. Given that all AE_X bits are disabled, what other internal conditions could force the AF flag to immediately re-assert (or prevent it from clearing)?

Any insights or recommendations would be greatly appreciated!

[JozefKozon]

Hi Vikas,

please double check the Alarm registers. These registers have address 0Eh to 12h. 

Please try to set all the AE_x bits to 1 again. 

With Best Regards,

Jozef

[vikasgupta]

Oops, sorry for the typo! The correct address is 0Eh to 12h. I just double-checked, and I did have it correct in my code, so it was just a mistake in my message.

[JozefKozon · Accepted solution]

Hi Vikas,

thank you for confirmation. Given the PCA2131 behavior described in the datasheet, and assuming AE_S/AE_M/AE_H/AE_D/AE_W are all 1. it does not look the RTC is legitimately re-triggering AF. Most likely cause is bitfield ordering mismatch. Could you please catch and share the scopes of the three reading, writing SPI messages? To confirm the timing and registers/bits written and read. 

With Best Regards,

Jozef

[vikasgupta]

Hi Jozef,

Thank you for your support and for pointing me in the right direction.

I checked the SPI messages using the picoscope and verified that the hardware values were correct. Following your suggestion, I debugged my code further and confirmed that the root cause was indeed a bitfield ordering mismatch.

I have fixed the mismatch, and the issue is now fully resolved. Thanks again for your help!

Best regards,
Vikas