Hi NXP Team,
I'm working with the project attached on MBDT using S32K3X8EVB-Q289.
I've encoutered a problem with freemaster that i don' know how to solve:
I'm quite sure that the port is available ... I've tried an other project without changing the cable connection and it works...
So i don't know where to look to find a solution...
BR,
Simon
Hello,
do you mean that the same port on the same cable works well with another FreeMASTER project? Then it must be something wrong with the communication settings in this particular project.
Try to avoid port probing in the project Options. Just select a real COM port Instead of COM_ALL.
If this does not help, please upload a FreeMASTER project which works well. I shall be able to see what is different.
Thanks,
Michal
Hi Michal,
I've find out, comparing the mexes files of the two project, that AIPS_PLAT_CLK was different...
In the bad project it's 80MHz, in the good one 120MHz...
Changing the value from 80 to 120 in the bad project and changing the FLEXCAN0CLK divider, in order to have 40MHz, make it works!
So my question is: Why the AIPS_PLAT_CLK interfeer with the freemaster comunication as freemaster is configured to work with LPUART13 (USB UART(serial) Interface on EVL BOARD) which have a AIPS_SLOW_CLK source? Is there something else that i'm missing?
I attached the Mex file of the good project, you ha compare with the one inside my zip to notice the differeces.
BR,
Simon
Hello,
I need to defer this issue to my colleagues in charge of S32K platform. I can only help with general FreeMASTER topic.
I'm not sure how the PLAT clock affects UART baudrate, but there is one trick that may help to confirm that this is the real issue.
In freemaster_cfg.h, you can define the FMSTR_DEBUG_TX to 1 and attach to a board with a plain terminal application (e.g. TeraTerm). You should see a sequence +©V printed periodically. by the board. If not, there is indeed a clock issue and you can attach a logic analyzer to SCI TX pin to see a real baudrate used.
Regards,
Michal