Hi Michal,
I've find out, comparing the mexes files of the two project, that AIPS_PLAT_CLK was different...
In the bad project it's 80MHz, in the good one 120MHz...
Changing the value from 80 to 120 in the bad project and changing the FLEXCAN0CLK divider, in order to have 40MHz, make it works!
So my question is: Why the AIPS_PLAT_CLK interfeer with the freemaster comunication as freemaster is configured to work with LPUART13 (USB UART(serial) Interface on EVL BOARD) which have a AIPS_SLOW_CLK source? Is there something else that i'm missing?
I attached the Mex file of the good project, you ha compare with the one inside my zip to notice the differeces.
BR,
Simon