Some questions to help with understanding the overall project situation -
1. Are both Release and Debug versions using the same data model (sdm | ldm) build configuration (affect data pointer size and addressing range in code)
2. Are both using the same linker .cmd file? IF not, why?
3. Are you accessing/using external memory and/or memory mapped devices with /CSx chip select signals? I have found, reported, issues with certain external I/O CS address spaces not working properly with respect to wait states, and it might be possible that when being slowly paced by USBTAP in debug mode it slows things enough to seem to work, but not when running full speed.
4. Are you using the Freescale "Beans" in your project? Do you have "Freeze Generated Code" selected?, Maybe forcing a complete rebuild/regen for the release version is needed?
5. What sorts of timers & other interrupts are you using - maybe your full speed operation is allowing interrupts to stack up and overflow how much available stack space you've alloted?
some of these may/may not apply to your situation, but to help understand possible causes, it is necessary to ask questions that touch on some of the usual suspects..
Mike