UM10204 Purpose of Min fall time requirement

[JamesK_2]

I'm referring to Table 11 "tf" requirement in the document linked here: I2C-bus specification and user manual (nxp.com)

If we have done thorough oscilloscope measurements and confirmed that our I2C interface is passing all other timing and voltage requirement but is failing the minimum fall time requirement for the Fast-mode is there any functional risk, assuming we also passing all EMC requirements for the product? I've looked through the NXP forums and have seen similar questions asked but none that I have seen have answered the specific question of what risk is posed if the fall time is faster than the spec allows but there are no other problems, like overshoot or non-monotonicity or timing violations.

Is it just to reduce the chances of EMC problems?  And if that is the case then why does Fast-mode Plus have the note stating that the minimum fall time spec is only required to be backwards compatible with fast-mode?

[xiangjun_rong]

Hi，

I suppose that the SCL fall time of your application can be less than the minimum fall time of SCL specified in the UM10204.pdf if we do not consider EMC feature of signal..

As you know that the I2C pin are open-drain pins, the falling time is dependent on the pin sink current spec and the pin capacitance.

maybe the data is latched with the falling edge of SCL, so the sharp falling edge of SCL does not take effect on the data latching.

This is my opinion.

Hope it can help you

BR

Xiangjun Rong

[JamesK_2]

Thank you for your quick response.  I have a question about one thing you said:

"maybe the data is latched with the falling edge of SCL, so the sharp falling edge of SCL does not take effect on the data latching"

Do you mean that if the edge is too fast the data might not latch? Or are you saying that the fast edge should not impact the data latching, and it should work fine?

Also, do you know how we could get in touch with the authors of this document?  I think that it would be great if they could add a note in the next revision describing the purpose of the minimum fall time requirement whether it is a serious functional risk or more for EMC mitigation.  I think it would help system integrators decide if their I2C designs are acceptable or require additional filtering components.

[xiangjun_rong]

Hi,

I mean that " the fast edge should not impact the data latching, and it should work fine".

For the following fig, I suppose it is okay to be less than the tfcl spec for the SCL signal of I2C.

But this is user manual, I can not track the author of UM10204.pdf, sorry.

BR

Xiangjun Rong