When using the fractional edge delay on the eFlexPWM, there is the requirement to not program pulses narrower than 3 clock cycles.
This requirement is only for channels using the fractional edge delay and does not apply to channels that are capable of fractional delay but not using the fractional delay.
PWM outputs may on some units power up to a logic 1 state when the analog micro-edge placer block is used. This is unavoidable and per the design. It is not a defect.
To get proper initialization when using the analog micro-edge placer block in the PWM, it is required power it up and run at least one PWM period where there is a PWM edge transition before enabling the PWM outputs. This will ensure that the PWM outputs are in a known state and allow the device to operate normally.