Question about interrupt functionality

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Question about interrupt functionality

Jump to solution
1,060 Views
timmeversmeyer
Contributor I

In my program I use a interrupt function which is triggered by a timer. The interrupt function is as follows:

 

#pragma interrupt alignsp saveall asm void TI1_Interrupt(void) {   /* Reset interrupt request flag */   bfclr       #0x8000, X:0x00f007  //do some calculations...      RTI }  

 

At the beginning the Interrupt request flag is set back. Then some calculations are done. The timer is running very fast. It could possible be that the time overflows before the functions has ended.

 

So my question is: is it possible that the interrupt function is called again before the function has been executed to the end? Or does the interrupt controller wait until the function has been executed before the interrupt function is called again?

Labels (1)
0 Kudos
1 Solution
802 Views
xiangjun_rong
NXP TechSupport
NXP TechSupport

Dear Timm,

Pls refer to the section 9.3.2.1 Normal Interrupt Processing and section 9.3.1 Interrupt Priority Structure in the DSP56800ERM.PDF, when an interrupt occurs, before the DSP core enter ISR, the CCPL(I1/I0 bits in SR register) is raised to be one higher than the level of the current interrupt, in other words, in this way the same interrupt can not interrupt again. For your case, I suppose you set the timer interrupt as 1, when the DSP enters ISR of Timer, the I1/I0 is added by 1 and becomes 2 automatically until the core exit the ISR, which will mask the interrupt source with 1 or 0 priority, so the same Timer interrupt event can not interrupt before the core exits the ISR.

BR

XiangJun Rong

View solution in original post

0 Kudos
1 Reply
803 Views
xiangjun_rong
NXP TechSupport
NXP TechSupport

Dear Timm,

Pls refer to the section 9.3.2.1 Normal Interrupt Processing and section 9.3.1 Interrupt Priority Structure in the DSP56800ERM.PDF, when an interrupt occurs, before the DSP core enter ISR, the CCPL(I1/I0 bits in SR register) is raised to be one higher than the level of the current interrupt, in other words, in this way the same interrupt can not interrupt again. For your case, I suppose you set the timer interrupt as 1, when the DSP enters ISR of Timer, the I1/I0 is added by 1 and becomes 2 automatically until the core exit the ISR, which will mask the interrupt source with 1 or 0 priority, so the same Timer interrupt event can not interrupt before the core exits the ISR.

BR

XiangJun Rong

0 Kudos