in my application i use an MC56F8037 DSC.
I am using input edges of secondary input external pin of Quad Timers as source of interrupts.
I have noticed that the input filter is not working.
In fact i don't see any effect on the latency by changing the sampling period and consecutive samples requid to agree parameters.
Is it the expected behaviour of this filter?
Is the interrupt working on raw signal?
Best Regards and thank you in advance
P.S: the Timer is configured as follows:
Count mode: Counting mode, count rising edges of primary source
Timer Channel Enabled (counter starts counting immediatelly after initialized): Yes
Primary source: Prescaler (IPB clock/ 32) , Secondary: Counter #1 input pin
Input polarity: True , Output polarity: True
Input capture mode: Load capture register on both edges of secondary input
Output mode: Asserted while counter is active
Count stop mode: Count repeatedly , Count length: Roll over , Count direction: Count up
Output enable (OFLAG to pin): No
Force OFLAG output at startup: No , Forced OFLAG value: 0
Master mode (broadcast compare event): Disable
Enable external OFLAG force (on broadcasted event): No
Co-channel initialization (on broadcasted event): No
Preload Control: 1: Never , Load Reg: 0
2: Never , Load Reg: 0
Interrupts: Overflow: Enabled
Input edge: Enabled
Cmp 1: Disabled
Cmp 2: Disabled
Input Filter: Input Signal Sampling [timer clocks] : 96
Consecutive Samples Required to Agree: 10
Input Signal Latency: 30.0625 us
#define QT_A2_CTRL_INIT 0x3A80U
#define QT_A2_SCR_INIT 0x14C0U
#define QT_A2_CMP1_INIT 0xFFDCU
#define QT_A2_FILT_INIT 0x0760U
Tazio, I don't know how you found the filter didn't work, but it should be working per you configuration. You can enable the capture interrupt and toggle a GPIO in the ISR. Observe the time between the edges of triggering input signal and the output of that GPIO, it should change as the configured latency changes.