NVT2002

[Pjanek]

HI NXP team,

I have to translate the signal from 5V to 1.8V, I have connected the VrefB- 5V and VrefA-1.8V

Question - 

Will it make any problem if I connect high-side portion to the I2C master and connect the low-side to I2C device ?

because I see in Application notes and Datasheet information show the low-side portion of the chip to be connected to the I2C master, while the high-side be the I2C device.

Thank you

[JozefKozon]

Hi Pjanek,

no, there is no issue. You can connect I2C master on high side. Please note, that EN is controlled by the Vref(B) logic levels.

With Best Regards,

Jozef

[PhenixYu]

Hello Kozon,  I also use the design, which is I2C master(NXP MCU 5V) on VerB, I2C device(3V3) on VerA, but I have one issue, which is as below: when I2C master send the message to the device, I found that the VerB side waveform is normal, but on VerA side, the waveform is distorted , and the high level(3V3) cannot be down to low level(0V) quickly, could you please help me resolve the issue? Thanks a lot!