MC56F84766 FlexCAN

[EngHuiPeng]

Can we have 2MBs for 1ID? If so, will both the IRQ flags be asserted for the 2MBs if they have received the message.

[ryanjarina]

Are the ID’s placed on the RxFiFo IDTableElement should also be configured into an RxMB buffer?

If so, how do I test the RxFiFo because if the RxMB can be serviced immediately, then I will not be able to see if the FiFo is working or not, is this correct?

[alex_yang]

Ryan Jarina wrote:

Are the ID’s placed on the RxFiFo IDTableElement should also be configured into an RxMB buffer?

If so, how do I test the RxFiFo because if the RxMB can be serviced immediately, then I will not be able to see if the FiFo is working or not, is this correct?

Let's bettter hold  a call meeting for this with customers. as the RxFIFO is little better complicated and misunderstanding.

[EngHuiPeng]

What will happen if a CAN MB IFLAG is asserted and is not yet serviced when another message of the same ID suddenly arrives?

Will the buffer be overwritten and flag it as overrun?

[EngHuiPeng]

To answer your above question:

1) All MBs were set as RX and they can receive the frame if the other MBs are disabled.

2) Yes, all IMASK were enabled.

3) When IRQ bit is set, IRQ bit will be cleared when the ISR function is serviced.

The message frame is sent out by the transmitting module as monitored using Vector CAN analyzer.

To test the queue, He just did a test to have a breakpoint inside the ISR function to check whether the other MBs, with the same ID setting, will be used or not.

The result showed that only 1 MB is used even if its status is “BUFFER FULL”.

[alex_yang]

Hi，

I used to wrote a demo with similar to customer’s scenario.

The occur of Rx overrun is depends on if CPU can catch up CAN receiving process.

That means, even if enable CAN queue or RxFIFO cannot guarantee no Rx overrun if CPU loading is too huge.(such as frequently servicing other interrupt). That’s a typical Producer-Consumer Problem.

More than one MB should be used in CAN Rx. and in the CAN interrupt handler, We should polling each receiving MB to see if them got a CAN frame, like below:

eg, MBx – Mby is used for CAN Rx:

void CAN_IRQ(void)

{

Check if MB with first priority overrun occur, if yes,  you might consider reduce CPU loading in system/app level.

If(MBx got a CAN frame)

{

Read data from buffer and make MBx to be empty for next receiving.

}

If(MBy got a CAN frame)

{

Read data from buffer and make MBy to be empty for next receiving.
}

If(…)

….

}

For TX,

Can you check if the frame is really send out or not?

[EngHuiPeng]

The customer is experiencing overrun, is this the only solution for overrun error, to try to use several MBs. It seems the status register is reporting BUS OFF and TX error warning. Is the bus off state generated only if there are too many transmission errors. The customer was testing the MB queue. IRMQ bit is enabled. He used 3 MBs (MBa,MBb,MBc) for 1 ID. He set a breakpoint on our CAN Rx driver. When break occurs, He checked the MBa, ok, buffer is full with data. Then He clear the IRQ flag and run the debugger again. After  15 seconds, paused the debugger, checked the MBa if data is still there, this is OK, data is still there. Run the debugger again, send a new message. Break occurs, check the MB, expected to use a different MB(MBb or MBc) that uses the same ID. Expected result is different, the queue did not work. The same MB,MBa, is used and the data is overwritten. Is there something wrong on his settings?

[alex_yang]

For Rx queue:

1. Check does MBa, MBb, Mbc all set as Rx MB?(this can be tested by:(for MBb:) disable MBa, MBc and see if MBb can receive frame)

2. Does MBa, MBb and MBc 's IMASK bit is enabled(enable interrupt)?

3. You mean when 1st frame arrived, software clear IRQ bit , when 2st frame arrived, software does not clear IRQ bit(for test)?

[xiangjunrong]

Hi, Hui,

From CAN theory, if you specify that two MBs receive the same ID, only the MB with low index can receive the packet and update it's IRQ flag. The MB with higher index can not receive the packet, it's IRQ flag is not updated either. For example, the MB3 and MB5 are set up to receive the same ID, when the packet arrives, only MB3 will receive the packet.

I copy the matching process here:

34.4.4 Matching process

The matching process scans the MB memory looking for Rx MBs programmed with the

same ID as the one received from the CAN bus. If the FIFO is enabled, the priority of

scanning can be selected between Mailboxes and FIFO filters. In any case, the matching

starts from the lowest number Message Buffer toward the higher ones. If no match is

Functional description

MC56F847xx Reference Manual, Rev. 2, 3/2014

940 Freescale Semiconductor, Inc.

found within the first structure then the other is scanned subsequently. In the event that

the FIFO is full, the matching algorithm will always look for a matching MB outside the

FIFO region.

As the frame is being received, it is stored in a hidden auxiliary MB called Rx Serial

Message Buffer (Rx SMB).

Hope it can help you.

BR

Xiangjun Rong

[ChrisN]

Your answer is correct, but it has nothing to do with "CAN theory". There are implementations where the receiving CAN controller tries to find a matching and available rx MB. Not the FlexCAN3, unfortunately. Here, the only option is to use the FIFO.