Configuration about MC56F72848 R/W two SPI FLASH.

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Configuration about MC56F72848 R/W two SPI FLASH.

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terrybogard
Contributor II

dear nxp expert,

is there any reference code or docs about MC56F72848 R/W two SPI FLASH? I have some questions about this application.

Q1: the SS is connected to VDD in Wire-OR mode, so in processor expert should the SS pin be enabled or just configured as GPIO output?

Q2: why the QSCI pin SS is not used in the Wire-OR mode figure?

Q3:what's the difference between the SS pin enabled and disabled when QSPI working? 

terrybogard_0-1616727783517.png

terrybogard_1-1616727989513.png

 

 

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

For the Fig 32-25, I think you do not need to care about the Wire-OR mode. In the Fig, you use GPIO from master SPI to select the slave.

When SS1 is low, the slave1 is selected, the MISO pin of slave1 spi is driven, in the case, SS2 pin is high, the MISO pin of slave2 spi is in high-impedance, so it can work.

When SS2 is low, the slave2 is selected, the MISO pin of slave2 spi is driven, in the case, SS1 pin is high, the MISO pin of slave1 spi is in high-impedance, so it can work.

Note that the SS1 and SS2 can not be low simultaneously.

Hope it can help you

BR

XiangJun Rong

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

For the Fig 32-25, I think you do not need to care about the Wire-OR mode. In the Fig, you use GPIO from master SPI to select the slave.

When SS1 is low, the slave1 is selected, the MISO pin of slave1 spi is driven, in the case, SS2 pin is high, the MISO pin of slave2 spi is in high-impedance, so it can work.

When SS2 is low, the slave2 is selected, the MISO pin of slave2 spi is driven, in the case, SS1 pin is high, the MISO pin of slave1 spi is in high-impedance, so it can work.

Note that the SS1 and SS2 can not be low simultaneously.

Hope it can help you

BR

XiangJun Rong

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