mcf5485 general purpose timer watchdog changing CNt after timer started

[flach_raymond]

Looking at the datasheet MCF5485, for the GMSn register for GPT 0 which I would like to use for the watchdog:

Bits        Name     Description

12           CE          Counter enable. Enables or resets the internal counter during internal timer modes only. CE must be set to enable these modes. If cleared, counter is held in reset.

0 Timer counter held in reset

1 Timer counter enabled

This bit is secondary to the timer mode select bits (TMS). If TMS is1XX, internal timer modes are

enabled. CE can then enable or reset the internal counter without changing the TMS field.

GPIO operation is also available in this mode.

The GCIRn register holds the prescaler and the CNT:

Bits        Name     Description

31–16     PRE       Prescaler. Prescale amount applied to internal counter (in clocks).

Note that in addition to other enable bits and field settings, the PRE field must be written as

non-zero to enable counter operation for all modes except the simple GPIO mode. A prescale of

0x0001 means one clock per count increment.

15–0       CNT       Count value. Sets number of prescaled counts applied to reference events, as follows:

IC—Field has no effect, internal counter starts at 0.

OC—Number of prescaled counts counted before creating output event.

PWM—Number of prescaled counts defining the PWM output period.

Internal Timer—Number of prescaled counts counted before timer (or watchdog) expires.

Reading this register only returns the programmed

My question centers around being able to change the timer period for the watchdog to a different value after initialization and startup of the watchdog.

If I change the GCIRn register CNT value, will it restart the timeout, or will the current value timeout finish first?

Writing a 0 to CE will hold the internal WD timer in reset. So I think if you want to reset the WD timer and set a new CNT value in the GCIRn register and then enable the timer counter with the CE bit, you could.

But maybe there is someone more familiar with the chip that could confirm this? I am looking for the correct sequence to follow.

[TomE · Accepted solution]

I think you'll have to reverse-engineer the timer.

Be very careful when writing registers with the timer running. It might not behave the same way every time. It might give you intermittent problems in the field.

I would read the following to say "Set TMS to zero before changing anything",

TMS: Timer mode select (and module enable).
000 Timer module not enabled. All timer operation is completely disabled. Control and status
registers are still accessible. This mode should be entered when the timer is to be re-configured,.

There are other possible complications. Some peripheral registers can only be written 32-bits at a time. Trying to perform 8 or 16 bit writes doesn't work, and can write garbage into the other fields. With other peripherals, writing to part of the register is essential for proper operation. For instance, for the PIT used in other Coldfire chips it is essential to perform byte-writes to the PCSR during interrupt service or the timing is reset. But nothing in the Reference has ever said that. The Register Definitions file only describes the PCSR as 16-bits, so that has always been misleading. You just have to spend a few days working this out for yourself, or you could read:

https://community.nxp.com/message/71442?commentID=71442#comment-71442 

So are the GPT registers 32-bits only, 32/16 or 3216/8? It doesn't say anywhere that I can find.

Tom

[flach_raymond]

I think I am going to run into issues, like you said. I think the best approach at this point will be for me to rewrite the watchdog timer software to work around the register limitations, and set the watchdog timeout to a fixed value at startup, say, 1 second, and having the interface handle longer duration timeouts by resetting the timer for the duration of the desired longer timeout period. Thank you for your reply.