mcf54416 bdm issues

[angelo_d]

Hi all,

i am testing a just soldered prototype board, with mcf54416. BDM seems wired correctly, but i can't connect to the target,

this using universal multilink and code warrior.

I re-checked BDM 26 pin connections, they seems correct (attached related diagram). I don't see any apparent issue in the diagram. Main voltages are there, clock is also there looking by scope, and cpu seems to try the SBF looking on dspi wires.

I am now wondering, what could be the most probable issue ?

- bad bga soldering (has been soldered in IR station)

- some other circuit error can block BDM ?

- wrong bdm tracks length ..

- ...

Every help is appreciated.

thanks

angelo

[angelo_d]

Hi Tom, many thanks.

BDM connection is clear now, i will recheck all signals in next prototype.

Btw, actually, my BDM connections should be good enough to have some replies from mcu, while i get nothing.

- mcu seems to be properly powered in all required voltages, i checked all voltages on BGA sides

- I see correct clock and freq on 25Mhz crystal (scope)

- I see also mcu attempts to read from external spi flash, when SBF is enabled (scope)

- i use P&E usb multilink universal, i see RESET and BKPT signals issued from the pod, and also, DSCLK and DSI signals are visible, but nothing is visible on DSO, like mcu is not responding at all (note, JTAG_EN pin is tied to gnd).

Every idea is appreciated.

thanks,

angelo

[angelo_d]

Hi,

have some updates ...

1) i programmed a serial flash with a sbf header and some code,

seems now cpu starts to respond ...

2) i see as in the attached picture that P&E pod sends a bdm cmd

READ CFG / STATUS, 0x2d80, and cpu replies with something

that seems a 0x0078.

Then, i don't see anything else happening.

Thanks,

angelo

[TomE]

ALLPST is only for the 196 pin package, and that is only because they didn't have enough pins to bring all four PST pins out. According to Note 22 on Table 5: "The ALLPST signal is available only on the 196 MAPBGA package and allows limited debug trace functionality compared to the 256 MAPBGA package.". You have all four PST pins, so use them.

Compare your design with the Reference Design. if you have a working Tower setup, compare the signals on there with your board.

What have you got BDM_RESET connected to? If that isn't connected then it won't work.

Tom

[angelo_d]

Hi Tom & Fang,

back on this after some time.

Seems i can't apply the Fang reduced BDM schematic, since i have MAPBGA256, and ALLPST pin is missing. What could i do ?

If ALLPST is only inportant to detect HALT cpu state, can is just use one pin only from PST0 to PST3 for this purpose ?

[angelo_d]

Hi Fang,

for the question about the 10k pull up, you should ask to freescale designers, since i copied it from TWR-MCF5441X (sch-26131.pdf) that i supposed correct. Anyway, i can just solder them as 4.7K  :smileyhappy:  Thanks for the diagram, will try it.

[TomE]

If your debug pod works on the Tower, then compare all the debug pod signals between it and your board.

Yes, as Fang says, watch out for pullups and pulldowns. Does this chip have BDM/JTAG selection options like some of the other ones do?

The Reference Design not matching the Reference Manuals and other design documents? Happens all the time. Sometimes different Reference Designs contradict each other on some design issues. For instance the Ref Designs commonly have pullup and pulldown resistors on different data bus pins to select the Reset Options. The manuals usually say "don't do that, use proper tri-state buffer instead".

Tom

[miduo]

Hi,

From the schematic, I do not know why you use the 10K pull-up for the BKPT, DSO, DSI and DSCLK pins. Actually we recommend to use 4.7K. And for pin 25, please let it open.

Attached is the schematic we used for BDM for you reference.