Hi Wolf
The M52233 has a core watchdog timer which can be disabled (writing 0 to CWCR) or programmed to generate an interrupt when it times out. Eg (with 2s timeout at 60MHz PLL):
#define WATCHDOG_2_SEC 0x30 // about 2 seconds at 60MHz bus
CWCR = (CWE | WATCHDOG_2_SEC | CWTA | CWTAVA | CWTIF); // activate watchdog
fnSetIntHandler(SW_WD_VECTOR, (unsigned char *)_sw_wdog_timeout); // enter watchdog interruot
IC_ICR_0_8 = (INTERRUPT_LEVEL_7 | INTERRUPT_PRIORITY_7);
IC_IMRL_0 &= ~(SW_WDG_PIF_INT_L | MASK_ALL_INT); // enable wacthdog interrupt
Note that the watchdog can not generate a reset directly so the interrupt is set to highest level, non-maskable so that it has highest chance of being able to operate.
To generate a reset when the watchdog fires, and its interrupt (_sw_wdog_timeout()) is called, the following can be performed:
RESET_RCR = SOFT_RST; // command a soft reset of the board
To stop the watchdog from firing it must be regularly reset by using the following feed sequence:
CWSR = 0x55; // retrigger the software watchdog
CWSR = 0xaa; // using this two byte sequence
Note that the watchdog should not be enabled when debugging since it fires when single stepping and causes loss of debugger control.
There are several other discussions about the pros and cons of the watchdog timer in the forum (eg.
http://forums.freescale.com/freescale/board/message?board.id=CFCOMM&message.id=2759&query.id=49225#M...Note that other parts, like the M52213 include a second watchdog called the Background Watchdog Timer, which is capable of directly generating a warm reset on underflow - this allows more reliable protection against SW errors.
Regards
Mark
www.uTasker.com
