> The multi-layer PCB is a management issue and cannot be resolved.
It will be resolved when you can never ship a working product and the company goes bankrupt and everybody loses their job. Easy.
Otherwise you need every square millimeter of both sides of the board covered with ground-plane and vias connecting all the ground areas on both sides together. Also filtering of all pins near the CPU.
How many dB are you failing by? If you're close (say 5dB) then you may be able to reduce the emissions by that much. If you're WAY over, then nothing will fix it except for good EM design, including multi-layer.
> The SSO will change the frequency slightly (1 - 2.5%) over time so that a peak frequency will not stand out and thus pass emissions.
Are you sure? We tried that on an MCF5329 and it didn't work as well as we thought.
On the quick "unofficial test" that looked for narrow emissions we could see the previous single spikes smeared out somewhat and turned into a "comb" of emissions.
The official emissions test doesn't look for very narrow peaks. It uses a bandpass filter. If the spread-spectrum "comb" is too narrow, all the energy can end up in the bandpass filter, resulting in the same result.
So you have to increase the spread spectrum modulation frequency, which is going to be limited by what the PLL can lock to.
If nobody else has done this, then you'll have to do all the tests yourself. Freescale don't give enough details of the PLL filter for you to model it, apart fomr the LOCK and UNLOCK frequency ranges. You'll be operating outside of the component specifications, so you'll have to reverse-engineer and then add your own safety margins.
> What is the highest frequency I can use for my external oscillator?
That information is in the Data Sheet.
Tom