Paul,
For a good description of the problem, have look at the information in the following link,
http://www.cvs.cx/Documents/CFPOD.pdf
It seems that Coldifre processors containing Revision A of the enhanced hardware debug module, require the BDM signals to be synchronised with the PSTCLK. In the above link, the author uses a XYLINX CPLD to implement D-Type flip flops which are clocked by the CPU Clock (PSTCLK). The flip flops ensure that changes to DSI and DSCLK (in particular) are synchronised to clock edges on the processor clock.
I have implemented a similar design to this and it works ok, however, if you want to re-work the TBLCF so that it works with processors such as the MCF5272, it is easier to use a single 74HC175 chip, rather than the CPLD. The problem is getting one that supports a fast enough clock speed. I found that the 74HC175N Chip from NXP (Philips) (RS Components 169-7481) works ok, but you do need a little series resistor between the output of the flip flop and the BDM connector (as per the design in the above attachment). For my purposes I only needed to buffer the DSI and DSCLK lines which make implementing a modification a bit easier.
I don't think you could perform the same synchronisation in software, unless you had a much faster processor than is used in the TBLCF and to be honest, it is easier implementing the hardware modification.
I hope this helps, let me know if you need more information.
Regards,
Michael