Stopping system clocks in debug mode with Code Warrior

[Eqqman]

Hello-

I've been trying to debug some code on the MCF52233 that makes use of an interrupt for PIT0.  With other architectures I've used the internal clocks are usually strictly controlled so that timer counters only increment as you advance opcode by opcode through your code.

With CW though we're finding that the clocks never stop running even though you would expect the device to be 'paused' when program execution halts due to a breakpoint or using the 'break' feature.  This is making it very difficult to debug code because we keep branching back to the ISR even before we've left the ISR to begin with.  To try and prevent this we push clearing the interrupt flag right down to before the RTE statement, but if 'too much' time has been spent looking at the code, we'll branch back to the start of the ISR before we can even execute the RTE.  Is there a way to get the PIT timers to only update their counters when instructions are actually being executed? 

[Eqqman]

Works like a charm, thanks!

I'm not used to having devices support that feature in hardware and I'd overlooked that bit.

[mjbcswitzerland · Accepted solution]

Hi

Set the DBG bit (bit 5) in the PIT Control and Status register to cause it to stop when in debug mode.

Regards

Mark

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