TVNAIDU,
I'd recommend the following design. It is relatively sophisticated, but it provides more available CPU time.
Two buffers of 54 samples each are need: while the calculation task processes the granted buffer, the other buffer is fill with the samples in the background.
The complete set of samples in the just filled buffer is as the following:
U0 I0 I1 ... I7 I7 I6 ... I0 U0
U1 I8 I9 ... I15 I15 I14 ... I8 U1
U2 I16 I17 ... I23 I23 I22 ... I16 U2
Assuming constant time interval between samples in the set, the average value of the two samples of the channel is related to the same time.
PIT ISR triggers the ADC for first sample in the set. Then, PIT ISR returns.
ADC ISR reads first sample from ADC to the buffer. Then, ADC ISR triggers the ADC for the second sample. Then, PIT ISR returns.
Next ADC ISR reads second sample from ADC to the buffer. Then, ADC ISR triggers the ADC for third sample. Then, PIT ISR returns.
...
When ADC ISR reads and fills the last sample (54-th) of the set, it updates number of the just filled (and granted) buffer. Then, ADC ISR releases the semapfore, which locks the calculation task.
Such a way, the sampling is suspended until next PIT interrupt.
Unlocked calculation task must process the granted buffer before the next buffer is granted. After processing of the granted buffer, the calculation task again pends on the semaphore.
I'd recommend, that, the calculation task use the fixed quantity of ~50 Hz periods of the mains voltage, instead of the exact 0.5 seconds. Start of each ~50 Hz period of the mains voltage can be detected by zero crossing of one of the well filtered ~50 Hz voltages. Such the arrangement keeps the accuracy of the measurement for the actual mains frequency below 50 Hz. Moreover, natural automatic tuning to 60 Hz is implemented.
To further save CPU time I'd recommend to assign both the task stacks and the buffers in the SRAM.