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Re: SRAM Data retention in low power modes
SRAM Data retention in low power modes
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SRAM Data retention in low power modes
01-12-2009
11:13 PM
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Cold_Fire_Start
Contributor I
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I need to know if SRAM data is retained during any or all of the low power modes:
WAIT, DOZE, STOP.
MCF52235RM
Rev. 5 09/2007 (9.4.2.2)
states that the SRAM is disabled in low power modes.
I understand that to mean no read or write access.
It does not say whether data is retained.
Can anyone verify if SRAM data written prior to entering a low power mode
is valid after a return to run mode?
previously posted in Codewarrior forum-oops
My Apologies for that.
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01-13-2009
08:42 PM
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RichTestardi
Senior Contributor II
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I use both WAIT and DOZE modes to conserve power, and then continue running from where I left off on wakeup via EPORT IRQ1*. SRAM and peripheral states (for peripherals I do not explicitly power down) are preserved. Is that what you are asking?
-- Rich
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01-13-2009
11:31 PM
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Cold_Fire_Start
Contributor I
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Yes Rich, that is what I needed to know.
We are looking at using the SRAM for non-volatile storage.
With a battery back-up.
Thank you for this response, as well as many others.
Your name has appeared in quite a few of the threads I've read.
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