Questions about the power up Sequencing of MCF54452(Coldfire)

[Kelben]

I read the DS of power up Sequencing, but I still do not understand the real sequency of EVDD/SDVDD and IVDD. Which one should be first? Or let's EVDD,SDVDD and IVDD power up together? One of our customers might have this potential issue. Now customer's power is slower than 50 V/millisecond. But I need to know the real power up Sequencing. Thanks.

3.3 Supply Voltage Sequencing

3.3.1 Power-Up Sequence

If EVDD/SDVDD are powered up with the IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected

to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD

must power up. The rise times on the power supplies should be slower than 50 V/millisecond to avoid turning on the internal

ESD protection clamp diodes.

[melissa_hunter]

Hi Kelben,

The power sequencing for most of the ColdFire MPUs is pretty much the same. Some of the early parts don't have the sense circuits that are present on MCF5445x. The sense circuits that keeps the pads tristated when IVDD is not powered were not on some of the earlier parts though, so on older parts the supplies had to come up more or less together. On MCF5445x, the timing isn't as stringent. Just bring up IVDD/PVDD after the IO supplies (both EVDD and SDVDD). You can ramp them together if you want or have a significant delay before IVDD comes up. Just don't bring up IVDD before EVDD and SDVDD.

Regards,

Melissa

[TomE]

Melissa wrote:

> Just don't bring up IVDD before EVDD and SDVDD.

What are the consequences of not following that advice? Will it damage the chip?

Kelben wrote:

> One of our customers might have this potential issue.

Given that boards have probably already been made, I'd suggest looking at adding two Schottky diodes from Ivdd to both Evdd and SDVdd. That way if Ivdd comes up first it will "drag" the other two up, obeying the "less that 0.4V" specification.

You may also need a (2k approx) resistor from Ivdd to ground to provide a path for the high reverse leakage currents of the diodes at high temperature. They may leak as much as 200uA each at 75C.

Tom

[TomE]

Search finds a very similar question with good answers from Freescale in 2010:

https://community.freescale.com/message/67779#67779

That's also a good answer from Hao Wang.

The MCF5475 and MCF5485 manuals are identical in the Supply Voltage Sequencing. The MCF54418 and MCF54452 manuals are the same. The MCF53017 is the most interesting as it has the "0.4V restriction" part printed in RED, like it is the first one to be edited this way (or it is VERY important :-).

These other manuals have recommendations that aren't in the one for your part. But they are also somewhat contradictory as they state both:

• Recommended that IVDD/PLL VDD should track EVDD/SD VDD up to 0.9V, then separate for completion of ramps.
• If EVDD/SD VDD are powered up with the IVDD at 0V, ...

So it recommends it tracks but it isn't required. Are there any advantages to the recommendation or disadvantages to not following it?

Maybe the latter condition forces all pins to high impedance, including some pins that otherwise wouldn't be in that state. So designs that power up that way might require external resistors (to establish a default state for external hardware) that wouldn't be necessary with the other power sequencing scheme.

I miss CPUs that had a single power supply (I'm also working with the i.MX53:-).

Tom

[cutworth]

Hi Kelben,

Please look at the MCF5475 DS, I find the power up sequence has more clear description. Basically the relationship is IVDD should not lead the EVDD, SD VDD, or PLL VDD by more than 0.4V during power ramp up or there is high current in the internal ESD protection diodes. And IVDD should not lag EVDD, SD VDD, or PLL VDD going low by more than 0.4V during power down or there is undesired high current in the ESD protection diodes.

I will copy Melissa Hunter in loop to double check if MCF5445x shares the same power up/down sequence.

Hao