Hi all,
found the following in the ColdFire CPU reference manual:
"...After the processor is granted the bus, it performs two longword read-bus cycles. The first longword at address 0x0000_0000 is loaded into the supervisor stack pointer and the second longword at address 0x0000_0004 is loaded into the program counter. After the initial instruction is fetched from memory, program execution begins at the address in the PC..."
In our application, the vector table is placed in flash starting from 0x00000000. The first entry (0x00000000) in the vector table is "__SP_AFTER_RESET" and the second entry (0x00000004) is "_startup" which is our starting point of software. So it well explains the program execution sequence.
But one thing I have not found the answer is the program execution under debugging mode. In this mode the vector table is placed in SRAM starting from 0x80000000, as we observed the program execution is still OK.
One explanation I guess would be under debug, BDM makes the CPU performs the two longword read-bus cycles from 0x80000000 as the vector table base address 0x80000000 is placed to the VBR (Vector table Base Register).
Another explanation would be:
"...After the processor is granted the bus, it performs two longword read-bus cycles. The first longword at address in VBR is loaded into the supervisor stack pointer and the second longword at address
(VBR+0x4) is loaded into the program counter. After the initial instruction is fetched from memory, program execution begins at the address in the PC..."
I'm just guessing anyway. Could anybody answer my questions?
Cheers,
