MPC83xx SPI sustained throughput

[George4444]

We are trying to use the SPI peripherial in Master mode to do data transfers of several Kilobytes at SPI clk rate of 22Mhz.  Our system clock is 266Mhz (csb).

More specifically, I am trying to get more details on the comment I found on page 19-6 (PDF page 1108) in the MPC8349EA  Reference Manual (MPC8349EARM.pdf, Rev 1).

What is the maximum sustained data rate for this peripheral?

What is a sustained SPI write?  Writing 2 bytes?

Thanks for the help,

George

[George4444]

I received a response via the online SR tool on this issue which is below.  I then replied with further questions.  I thought I would post here incase others are looking.

MY FURHTER QUESTIONS:

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Hi Alexander,

What does it mean, "gaps should be inserted between multiple characters to keep from exceeding the maximum sustained data rate."

Are you saying, the maximum sustained data rate is 5Mbps (at csb=266).  So this means I don't need to insert gaps if I run my SCLK at 5Mhz?

If I run my SCLK at 22Mhz, does this mean I need to insert "Time" gaps between every pair of bytes since the SPI peripheral has a 2 byte buffer?

Please elaborate.

Thanks,

George

FREESCALE RESPONSE TO INITIAL QUESTIONS:

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Dear George,

In reply to your Service Request SR 1-702443694:

MPC8349 Reference Manual says:

The maximum sustained data rate that the SPI supports is system (csb) clock/50. However, the SPI can transfer a single character at much higher rates—system clock/4 in master mode and system clock/2 in slave mode. Gaps should be inserted between multiple characters to keep from exceeding the maximum sustained data rate.

For 266 Mhz csb it will be 266/50 = ~ 5 Mbps.

Thank you for your interest in Freescale Semiconductor products and for the opportunity to serve you.

Should you need to contact us with regard to this message, please see the notes below.

Best Regards,

Alexander

Technical Support

Freescale Semiconductor