Could it be this:
23.3.3 Processor Bus Output Timing Specifications
NOTE
Above 48 MHz, the memory bus may need to be configured for one wait
state. It is the responsibility of the user to determine the actual frequency at
which to insert a wait state since this depends on the access time of SRAM
or SDRAM used in a particular system implementation.
The Debugger might be trying to access external memory and may need to be changed to add the wait states when it first programs the CPU.
You may need to reprogram the SDRAM controller for the higher speed.
You should also check to see if there are any known issues with the debugger when you speed the CPU up - with the Debugger manufacturer.
Also check the Duty Cycle of the new clock you're generating. It must be better than 45/55% to meet the CPU specs. Also the rise time:
23.3.1 Clock Input and Output Timing Specifications
If you program a CPU at 48MHz and then restrap it to 62.5MHz does it run? This might help to isolate the problem as being with the CPU or with the debugger.
Tom