Just a quick question about the pin connections on the clocking module:
What do you suggest I do with the PLLTEST pin (D15)? I am using the eval kit schematic as a reference however this pin is just floating.... Is this correct?
Also should I tie the TEST pin (ab20) to ground?
According to the Data Sheet and the Reference Manual, PLLTEST is an Output pin, and TEST is an input with a built-in pull-down. Apart from listing this information in the pin tables, the manuals don't document what these pins do, what they're for and what you should do with them.
So PLLTEST should be left open, and as for TEST, when it doubt, copy what the Reference Designs do.
Which in this case is "connect everything into a monster FPGA, including TEST", which hides what they're doing with it. Is there any documentation on what the FPGA has inside it?
Time to do some "Document Archaeology". The manuals are cut-and-pasted from previous ones, and sometimes the earlier ones might give more details. Or different details.
Searching for "PLLTEST" on Freescale finds mention in 15 documents. It found a match in the MCF5329 manual, but that's a "false positive" as that word isn't in there. I've seen this before.
The Tower Schematic for the MCF5441X is REALLY interesting as it has pin L12 called "PLLTEST/GND25" on the schematic, but this pin is NOT called "PLLTEST" anywhere in the Reference Manual, but is documented as a ground. So it is a "secret input test pin" only documented on the Reference Schematic. So the PLLTEST pin on the MCF5441X and MCF5445X seem to be completely different, as one is an input and one is an output. It might be a documentation error.
Interestingly, the "TEST" input on the MCF5441X is documented in its Reference Manual to be the same as the MCF5445X. It is an input with a built-in pulldown. However there's a warning in that manual stating "(this signal must be grounded)" that is present on the TEST Section of the table. It looks like this warning was removed in the MCF5445X manual when the PLLTEST output pin was added to that section. Just because the warning has been edited out doesn't mean it doesn't apply.
I'd suggest grounding TEST through a zero-ohm resistor, so you can remove that resistor if you ever find you need to. Also bring PLLTEST out to a test point in case you need to do something with it, although the fact that it is floating in the Reference Design is a farily good hint. When you make the board, test PLLTEST to see if it is a floating input, pulled-down input or a driven output. In the unlikely event you find it doesn't match the manual, lodge a Service Request on it and tell us here.
See if you can find any other reference designs. They often contradict each other and often do things that seem to disobey the manuals.