MCF5329 LCD controller

[lhemmen]

Has anyone sucessfully configured the LCD controller for a panel other than the sharp displays that are listed in the example code from freescale?  I have gone over the manual and the lcd example code with the data sheets from sharp and I can not recreate the timing values that are listed in the software. 

I have been trying to interface two LG phillips displays and I am not making any head way with the configuration.  If any one has any helpful advise it would be much appreciated.

[RafW]

What's the DE mode ? Is it for LCD or for MCF uP?

[Mikee]

We are using a NEC 6.5" display VGA.
We are not using the DE mode.
I would suggest not to use the DE mode.
This means tying the line high or low or float depending on your data sheet.
Then you have to pay special attention to the timing diagrams and specs for the display.
I used debug from freescale to poke values into the registers of the CRT controller until I got the timing right. A logic analyser helps a lot too.
After I got this right we made a new table for PEG to use for the NEC 6.5 display and things are working fine now. But it did take a while.

[CANtronik]

I'm looking for some help / past experience with connecting a WVGA (800x480) DE mode LCD to the 5329 device. I can't decide from this thread whether DE mode is an option or not with the controller in the 5329. The LCD I am wanting to use does not have HSYNC/VSYNC and will only accept DE mode. I'm not expert enough on TFT LCD's to know the difference but I have a QVGA working fine with my Cobra 5329 Eval Board and now I want to connect the WVGA screen.

It would be much appreciated if someone can advise.

Best regards,

Dave

Message Edited by CANtronik on 2007-03-2602:29 PM

Message Edited by CANtronik on 2007-03-2602:34 PM

[nafiton]

Hello.

We have success with a VGA display (DE Mode) connected directly to  the 5329 LCD controller (after apply the priority thing :smileyhappy:. Now we need to connect another TFT VGA display (DE mode) through a LVDS connection.

We are seeing already the data on the display but we have a blue line just on the first screen vertical line.
The problem seems to be a lost clock cycle on the LCD_SLCK signal just before LCD_OE is going active.
http://www.horus.es/sclk.jpg links goes to a oscyllocope photo where you can see how SCLK is blocked during one cycle just before OE goes active.

We don´t find anything on the reference manual that explain this behaviour. Any idea what are we missing?

Thank you ,

naf

[nafiton]

Hi.

We contacted with FreeScale support and get a workaround to this problem.

In 32 bpp mode, the LCD controller resets the internal logic before a line is scanned. Our connecction, beeing a LVDS serialization, needs a stable clock. So, when the LCD_SCLK was reteined, the LVDS signals got wrong data and the result was a bad line starter colors.

They tell us It does not happen working at 16bpp. We are working now so, and working well.

Thanks

[will76]

Hi,

I'm working with the MCF5329EVB and I'm beginning to work with the LCD controller. I have a sharp dispay that I bought from LogicPD. You are doing comparison between several LCD. display. Maybe, you have succeeded in configuring the sharp display..
If so, could you help me in configuring it?

Thanks,
Best regards,
William

[Mikee]

Are you using the Freescale (Logic PD ) EVB and their display kit?  If so, be aware that the DE mode can not be used because that output is used for LCD VCC ENABLE and not the DE function. To compound the problem they did not initalize that bit as an IO function but as a graphics function, so the signal becomes active during display data and can turn on/off the VCC to the LCD!

I have found that some registers don't have enough bits to allow some of the front and back porch times for some displays. This would force the issue of using the DE mode.

Good luck!

 Mike

[lhemmen]

Yes we are using the Freescale EVB but not Logic's display kit.  I have talked to Logic PD about the VCC Enable, and I think we have that worked out.  So far none of the values that I come up with for our panels work, the closest I can get is a display were one pixel write causes a whole column to be changed which means my vertical timing is off?  I have tried to come up with the values that Freescale uses for the sharp displays in the LCD example code but I haven't had the best of luck duplicating their values either. 

[Mikee]

Well, too many questions to ask about it here. What size display? what resoulution? What display mode are you in ( 8 bit)? I assume you have a scope to look at the V & H sync timing. The way I did my trial error was to load Freescale DEBUG. This allows you to access the LCD register on the fly. I kept playing with the register values until I had set them up correctly. You are probably doing this already and beyond me helping you, but I would take a good look at the siganls with a logic analyzer or good digital scope.

Good luck.

[lhemmen]

Ok here we go,  two panels 800x600 and 640x480 by LG Philips, display mode 16-bit.  I have been watching timing on a 4 channel digital scope and my de and hsync are looking good.  vsync I am catching heck getting it close.  I have both displays working on an epson S1D13505 LCD controller just fine so I am trying to compare my timing between the two right now.

You've gotta love LCD controllers I only need to change them every few years, just long enough to forget all of the gotchas that I had to endure the last time.

[Mikee]

LOL! I did mine 4 months ago and I forgot everything. One thing I did note: your are using DE mode not fixed? I would not use DE mode unless the registers aren't big enough to hold your timing. Also make sure you have the LCD controller as highest priority in the CROSSBAR switch register.

Keep plugging away, you will get it.