MCF5328 with DDR & Flash

cancel
Showing results for 
Search instead for 
Did you mean: 

MCF5328 with DDR & Flash

Jump to solution
426 Views
Soos
Contributor II

Hi,

I am facing a strange problem with MCF5328, DDR Micron MT46V16M16CY (16Mx16) & Flash SST39VF1601. All these three are BGA package. Initially I thought it is solder problem under BGA chip. But both flash & DDR do not work together. If DDR is removed, flash works fine. DDR always work good in any case. I have used 22 ohm for all signals going to DDR just next to DDR. Only address bus A(0)-A(15) is common to both chips. It goes directly from processor (through 22 ohm) to DDR & from processor through buffer (level shifter) to flash.

It might be a layout problem, but before I go for new 4-layer board, I want to make sure what other precautions I need to take.

If anybody has faced similar problem, please advice.

Thanks.

Labels (1)
0 Kudos
1 Solution
149 Views
TomE
Specialist I

Make sure you have the MSCR_FLEXBUS and MSCR_SDRAM registers set to the right values. These registers ARE NOT DOCUMENTED PROPERLY. They perform the same "drive-level adjustment" as all the other "drive level" registers do and act the same way. They've just given the registers and the bits in them poor names that don't properly describe what they do.

 

Read the following for details.

 

https://community.freescale.com/message/66438#66438

 

https://community.freescale.com/thread/66541

 

Make sure your "split bus setup" is properly done, including the registers involved with this.

 

Download *ALL* the development board schematics. I have at least three for three different development boards, and I know Freescale has a fourth one they used internally. Representative file names (for searching):

 

  POSREFDESIGNSCH.pdf

    http://cache.freescale.com/files/soft_dev_tools/hardware_tools/printed_circuit_boards_for_reference_...

 

  MCF5329_REF_DES.zip

  1001664B_MCF5329_Schematic.pdf

 

Compare all the bus signals with what you've done. Especially the byte-lane selects, they're easy to get wrong.

 

On reflection there's another thing you should check:

 

> & from processor through buffer (level shifter) to flash.


"Level shifter"? It is a lot easier if you use FLASH that uses the same VCC that the DDR does.

 

Do you have the same "level shifter" in the data bus from the FLASH to the CPU?

 

I'm guessing you copied the "POSREFDESIGNSCH.pdf" which has shifters everywhere. Make sure the bus-direction-control signals are working properly.

 

You should be able to load some test programs (that you write yourself) into the Static RAM that can try some simple SDRAM and FLASH tests over the bus to try and isolate the specific signal problem you're having. At the least you can have that program in a loop running bus cycles so you can look at the signals with an oscilloscope.

 

Tom

 

View solution in original post

0 Kudos
2 Replies
150 Views
TomE
Specialist I

Make sure you have the MSCR_FLEXBUS and MSCR_SDRAM registers set to the right values. These registers ARE NOT DOCUMENTED PROPERLY. They perform the same "drive-level adjustment" as all the other "drive level" registers do and act the same way. They've just given the registers and the bits in them poor names that don't properly describe what they do.

 

Read the following for details.

 

https://community.freescale.com/message/66438#66438

 

https://community.freescale.com/thread/66541

 

Make sure your "split bus setup" is properly done, including the registers involved with this.

 

Download *ALL* the development board schematics. I have at least three for three different development boards, and I know Freescale has a fourth one they used internally. Representative file names (for searching):

 

  POSREFDESIGNSCH.pdf

    http://cache.freescale.com/files/soft_dev_tools/hardware_tools/printed_circuit_boards_for_reference_...

 

  MCF5329_REF_DES.zip

  1001664B_MCF5329_Schematic.pdf

 

Compare all the bus signals with what you've done. Especially the byte-lane selects, they're easy to get wrong.

 

On reflection there's another thing you should check:

 

> & from processor through buffer (level shifter) to flash.


"Level shifter"? It is a lot easier if you use FLASH that uses the same VCC that the DDR does.

 

Do you have the same "level shifter" in the data bus from the FLASH to the CPU?

 

I'm guessing you copied the "POSREFDESIGNSCH.pdf" which has shifters everywhere. Make sure the bus-direction-control signals are working properly.

 

You should be able to load some test programs (that you write yourself) into the Static RAM that can try some simple SDRAM and FLASH tests over the bus to try and isolate the specific signal problem you're having. At the least you can have that program in a loop running bus cycles so you can look at the signals with an oscilloscope.

 

Tom

 

View solution in original post

0 Kudos
149 Views
Soos
Contributor II

Hi Tom,

Many thanks for your suggestions/advice. 

While reviewing MSCR_FLEXBUS and MSCR_SDRAM registers, we found there one mistake.

When we corrected it, all boards started working.

Your reply was very helpful.

We were about to go for new layout, thinking the problem is with the layout.

Regards,

Suhas

0 Kudos