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- MCF51QE high internal reference clock
MCF51QE high internal reference clock
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MCF51QE high internal reference clock
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Hi,
I recently started working with a product incorporating the MCF51QE128. According to the data sheet the typical value for the internal reference clock is 32.768 kHz. However, when I try to verify this by measuring on GPIO toggled by a TPM interrupt the derived clock appears to be 38.4 kHz. The trim value is loaded from flash address 0x03FF (0x0061). Other settings are:
DRS = 00
DMX32 = 0
BDIV = 0
The debugger outputs "Bus Freq = 9837KHz" which also points to 38.4 kHz reference clock.
Is the trim value wrong? Or am I missing something else?
Best Regards,
Johan
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Software or hardware debugger? When the hardware debugger is connected, it uses a default trim value of 0x80.
When running without the debugger, it loads from the Flash IFR which is documented as being at 0x3ff, but is also documented as being UNREADABLE from the debugger or from user code. The only way to find what value is written in there is to have the chip run standalone and then print what got loaded into ICSTRM.
Search this forum for "IFT TRIM" and other keywords. This one might be useful as it details (amongst other things) how some programming tools have to be set up to change (or not change) the stored values:
https://community.nxp.com/message/78618?commentID=78618#comment-78618
You can always reload ICSTRM with values from some other NV storage in your product if that is more convenient.
Tom
