MCF 52259 FlexCAN problem, source code supplied

[Liljo]

Hello !

I have some trouble with the FlexCAN on ColdFire, hope someone can help me out

Sometimes the FlexCAN sends multiple frames on to the network even though we only send one frame by the CAN driver (we are using the drivers supplied with CodeWarrior). This seems to happened randomly it could work fine a long time then suddenly all frames sent are duplicated.

We have also seen bursts of messages (with the same message) causing 100% busload.

Have done a lot of debugging, for example a breakpoint at the start of the send service in the CAN driver and a breakpoint at the end i can see that 2 frames are sent at each call to the send routine.

However if i set another breakpoint just after writing 0xC to the CODE field then only one frame is sent.

Anyone have an idea of what could be wrong? I have not found any errata on this problem.

I supply the send service in the driver, we are only using one mailbox for TX.

int8 FlexCANSendDataPoll(uint8 *pData, uint8 u8Size, uint32 u32ID, uint8 u8MB)
{
    uint8 u8Counter;
    uint8 *pDataPointer;
    uint32 u32Rescue = 0;
    tFlexCANMB *BuffPtr;
    uint16 temp = 0;

    /*Set the buffer pointer*/
    BuffPtr = &MCF_FLEXCAN_BUFFERS.MB0 + u8MB;

    (*BuffPtr).u16CtrlStat = MB_CTRLSTAT_CODE(0x8);
    if (!(u32ID & FLEXCAN_EXTENDEDID(0)))
    {
        /* Standard ID */
        (*BuffPtr).u32ID.u32ExtID = MB_STANDARD_ID(u32ID);
    }
    else
    {
        (*BuffPtr).u32ID.u32ExtID = MB_EXTENDED_ID(u32ID - FLEXCAN_EXTENDEDID(0));
        temp |= (MB_CTRLSTAT_SRR | MB_CTRLSTAT_IDE);
    }
    pDataPointer = &((*BuffPtr).u8Data0);
    for (u8Counter = 0; u8Counter < u8Size; u8Counter++)
    {
        *(pDataPointer++) = *(pData++);
    }

    temp |= MB_CTRLSTAT_LENGTH(u8Size);

    (*BuffPtr).u16CtrlStat = MB_CTRLSTAT_CODE(0xC) | temp;

    while(!(MCF_FlexCAN_IFLAG & (1<<u8MB)))
    {
        if (u32Rescue++ == RESCUE_VALUE)
            return 0;
    }

    /* Clear interrupt flag */
    MCF_FlexCAN_IFLAG = (1<<u8MB);

    return 1;
}

[Kan]

The EXTAL pin is good otherwise you program can't boot at all.Maybe the crystal connected at EXTAL pin is not stable as it is supposed to be.In the validation for flexCAN we also used EXTAL as the clock source but no error occurs as your case.Anyway,you should choose a stable clock source for that module.The system clock is a better choice if you are not sure of the external clock.

[Robotics]

Hello, I have the same problem about FlexCan. I notice that if I don't use PLL then  EXTAL works fine. If I use PLL and FlexCan with the EXTAL doesn't woks fine. Always with the same cpu speed.

I also see that it doen't happen if you freeze the bus previous to made the changes to send, independent of the PLL or EXTAL for FlexCan.

¿ What clock uses the arbitration sequence ? ¿ The selected clock  or always FSys/2 ?

Regards.

[Robotics]

Hello,

Now it woks fine !!

If you use EXTAL for FlexCan, 48MHz and PLL for CPU with the same speed 48MHz, there will be problems with frames send twice.

If you use EXTAL for FlexCan and PLL up to 66, 80 MHz works fine. It seems a problem with the sync beetween Flexcan frequency and FSys.

For this reason when I didn't use the PLL (same EXTAL clock for FSys and FlexCan works fine).

¿ Is that right ?

Thanks !!

[TomE]

That looks like something that should be in the Errata for this chip.

Except I can't find any errata documents for the MCF5225x chips on Freescale's sites. Anyone know where they are?

[JulienP]

Hello sir,

It seems I'm running into the same problem as you, but in my case the frames are sent once or many times (more than 50), depending of the data. In that case, the ERRCNT is increasing and BIT1ERR bit is set, as BUS OFF (but interrupt disabled) bit. The thing I can't understand is why does it depend of the data I'm sending? For example, 0x.........BB works fine, but 0x.........CC is sent many times. Do you think it can be somethink like you?

[Kan]

No problem with the code.I suggest that you also enable the ERR&BOFF interrupts to check if any error occur when the case happened.In the message validation part of CAN 2.0A/B , the auto retransmission for corrupted message will occur as soon as the bus is idle.

[Liljo]

OK, Thanks Kan.

I never get any error flags and no error frames are sent.

However i changed the clock source from EXTAL to system clock and now it seems to work.

I was able to run all my test suites without any duplicate frames or 100% load.

Could my previous problems have been caused by a bad EXTAL ???????

[kef]

---

Liljo wrote:

Sometimes the FlexCAN sends multiple frames on to the network even though we only send one frame by the CAN driver (we are using the drivers supplied with CodeWarrior). This seems to happened randomly it could work fine a long time then suddenly all frames sent are duplicated.

We have also seen bursts of messages (with the same message) causing 100% busload.

---

Not familiar with FlexCAN, but sounds like sometimes your node detects errors and retransmits messages twice or more times.

[Liljo]

No error condition is indiacted by the flexcan registers.

When it enters the state where it sends duplicate messages it does so continuosly, all tx messages are duplicated, then if i do a hardware reset it comes back to normal operation again and only sends one message as it should.

[Kan]

Can you also provide the code for initializing flexCAN?

[Liljo]

Hello Kan,

Thanks for responding,

To initialise i call the following function:

(The definition of the other functions follows)

void initialiseCAN( void )
{
    U8 i;

    FlexCANInit();

    FlexCANRegisterRxCallback( canRxCallback );

    for( i = 0; i<8 /*12*/; i++ )
    {
        FlexCANSetMask( i, 0);
        FlexCANSetMBforRx( i, 0x7FF );
        FlexCANEnableMBInterrupt( i, 0 );
    }
}

void FlexCANInit(void )
{
    /* Register Initialization */
    FLEXCAN_GPIO_INIT();
    MCF_FlexCAN_CANMCR = MCF_FlexCAN_CANMCR_SOFTRST;
    while ((MCF_FlexCAN_CANMCR & MCF_FlexCAN_CANMCR_SOFTRST) != 0x00)
        ;
    MCF_FlexCAN_CANMCR = MCF_FlexCAN_CANMCR_MDIS | MCF_FlexCAN_CANMCR_MAXMB(0xF);
    while ((MCF_FlexCAN_CANMCR & MCF_FlexCAN_CANMCR_NOTRDY) !=
            MCF_FlexCAN_CANMCR_NOTRDY);

        /* Setup bit timing:
         * Baudrate: 125 Kbit/s => BRP = 23
         * PROPAG = 1 => 1-1 = 0
         * PHASE1 == PHASE 2 = 7 => 7-1=6
         * SJW = 4 => 4-1 = 3
         */
      MCF_FlexCAN_CANCTRL = MCF_FlexCAN_CANCTRL_PRESDIV(23)|
                     MCF_FlexCAN_CANCTRL_RJW(3)|
                     MCF_FlexCAN_CANCTRL_PSEG1(6)|
                     MCF_FlexCAN_CANCTRL_PSEG2(6)|
                     MCF_FlexCAN_CANCTRL_ERRMSK|
                     MCF_FlexCAN_CANCTRL_BOFFMSK|
                     MCF_FlexCAN_CANCTRL_PROPSEG(0) |
                     1 << 4;

    /*
     * MBuf Initialization
    */
    MCF_FLEXCAN_BUFFERS.MB0.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB1.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB2.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB3.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB4.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB5.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB6.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB7.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB8.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB9.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB10.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB11.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB12.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB13.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB14.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);
    MCF_FLEXCAN_BUFFERS.MB15.u16CtrlStat = MB_CTRLSTAT_CODE(0x0);

    MCF_FlexCAN_RXGMASK  = 0;

    MCF_FlexCAN_CANMCR &= ~(MCF_FlexCAN_CANMCR_MDIS);
    while ((MCF_FlexCAN_CANMCR & MCF_FlexCAN_CANMCR_NOTRDY) != 0x00)
        ;

    MCF_FlexCAN_IMASK = 0x00;

    MCF_INTC1_ICR08 = MCF_INTC_ICR_IL(2) | MCF_INTC_ICR_IP(0);
    MCF_INTC1_ICR09 = MCF_INTC_ICR_IL(2) | MCF_INTC_ICR_IP(1);
    MCF_INTC1_ICR10 = MCF_INTC_ICR_IL(2) | MCF_INTC_ICR_IP(2);
    MCF_INTC1_ICR11 = MCF_INTC_ICR_IL(2) | MCF_INTC_ICR_IP(3);
    MCF_INTC1_ICR12 = MCF_INTC_ICR_IL(2) | MCF_INTC_ICR_IP(4);
    MCF_INTC1_ICR13 = MCF_INTC_ICR_IL(2) | MCF_INTC_ICR_IP(5);
    MCF_INTC1_ICR14 = MCF_INTC_ICR_IL(2) | MCF_INTC_ICR_IP(6);
    MCF_INTC1_ICR15 = MCF_INTC_ICR_IL(2) | MCF_INTC_ICR_IP(7);
    MCF_INTC1_ICR16 = MCF_INTC_ICR_IL(4) | MCF_INTC_ICR_IP(0);
    MCF_INTC1_ICR17 = MCF_INTC_ICR_IL(4) | MCF_INTC_ICR_IP(1);
    MCF_INTC1_ICR18 = MCF_INTC_ICR_IL(4) | MCF_INTC_ICR_IP(2);
    MCF_INTC1_ICR19 = MCF_INTC_ICR_IL(4) | MCF_INTC_ICR_IP(3);
    MCF_INTC1_ICR20 = MCF_INTC_ICR_IL(4) | MCF_INTC_ICR_IP(4);
    MCF_INTC1_ICR21 = MCF_INTC_ICR_IL(4) | MCF_INTC_ICR_IP(5);
    MCF_INTC1_ICR22 = MCF_INTC_ICR_IL(4) | MCF_INTC_ICR_IP(6);
    MCF_INTC1_ICR23 = MCF_INTC_ICR_IL(4) | MCF_INTC_ICR_IP(7);
    MCF_INTC1_ICR24 = MCF_INTC_ICR_IL(5) | MCF_INTC_ICR_IP(0);
    MCF_INTC1_ICR25 = MCF_INTC_ICR_IL(5) | MCF_INTC_ICR_IP(1);

    MCF_INTC1_IMRL &= ~(MCF_INTC_IMRL_INT_MASK25|MCF_INTC_IMRL_INT_MASK24|
                       MCF_INTC_IMRL_INT_MASK23|MCF_INTC_IMRL_INT_MASK22|
                       MCF_INTC_IMRL_INT_MASK21|MCF_INTC_IMRL_INT_MASK20|
                       MCF_INTC_IMRL_INT_MASK19|MCF_INTC_IMRL_INT_MASK18|
                       MCF_INTC_IMRL_INT_MASK17|MCF_INTC_IMRL_INT_MASK16|
                       MCF_INTC_IMRL_INT_MASK15|MCF_INTC_IMRL_INT_MASK14|
                       MCF_INTC_IMRL_INT_MASK13|MCF_INTC_IMRL_INT_MASK12|
                       MCF_INTC_IMRL_INT_MASK11|MCF_INTC_IMRL_INT_MASK10|
                       MCF_INTC_IMRL_INT_MASK9 |MCF_INTC_IMRL_INT_MASK8 |
                       MCF_INTC_IMRL_MASKALL);
    return;
}