M5223X Ethernet DMA influences

[mjbcswitzerland]

Hi All

We are trying to work out the following effect.

1. PIT1 is set up to interrupt every 50us. The interrupt routine lasts 8us in which is toggles a port (to generate 10kHz square wave) and then toggles another port 10 times (this generates a short signal with about 1.5MHz frequency). The PIT1 interrupt has NMI status so can not be blocked. The frequency and mark-space is thus very stable.

2. Every 50ms a memory transfer is made (1500 bytes from FLASH to RAM) using DMA. This takes about 200us and there are thus about 4 PIT1 time output port edges. This is repeated with the CPU in normal operating mode and also using the WAIT mode (the CPU is stopped whenever there are no interrupts to process).

The first intermediate result shows that the memory transfer using DMA doesn't have any great effect on the accuracy of the NMI timer interrupt - there is no noticable increase in jitter. When the memory transfer DMA is in operate it is seen that the 1.5MHz output slows down slightly - it is seen that the instructions are interleaved with DMA accesses (about one DMA cycle steal for 4 instructions approximately).
The result is identical using the low power MODE mode or not.

3. The test was repeated with a web server serving pages.
There are possible 3 results each time the web page is refreshed:
a. No change in the 10kHz output. This is valid for about 80% of the tests. (A logic analyser was used to trigger on changes of waveform of +/-1us.
b. about 5% of the time the mark space ratio of the wavform would change slightly - instead of 50us/50us it would be 48us/52us, indicating that one of the interrupts was delayed by around 2us (the period was not changed though).
c. about 15% of the time the mark space ratio of the waveform would change more - instead of 50us/50us it would be 37us/63us, indicating that one of the interrupts was delayed by around 13us (the period was not changed though).

This was also consistent with or without the DMA memory transfer test as detailed in 2 and with or without the WAIT mode.

This seems to suggest that the DMA operation of the Ethernet controller can delay the interrupt (note that no other NMI interrupts are used, so the Timer interrupt can not be delayed due to priorities).

Can this behaviour be explained or controlled in any way?

Regards

Mark

www.uTasker.com


Message Edited by mjbcswitzerland on 2008-08-05 04:08 PM

[admin]

Hi Mark,

My guess is, this is a side effect of the selected internal bus arbitration algorithm. It's described in the System Control Module (SCM) section of the manual. I think what happens is the DMA controller of the FEC takes control of the bus preventing the CPU from serving the interrupt.
I'm not sure how many different busses there are within the MCU, and which ones are shared between the CPU and the FEC's DMA, but one of them must be the source of contention. Try different bus arbitration algorithms and see what happens.

Regards,
- mike

[mjbcswitzerland]

Hi Mike

Thanks. I have seen the registers that can be modified and may get a chance to experiment later with them.

Regards

Mark