LCD segment addressing problem with the MCF51EM128CLL MCU

[clivebuxton]

Has anyone had any issues addressing a segmented LCD display from a  MCF51EM128CLL ?

We are having an issue whereby some of the chosen segments are not responding as programmed to the LCD registers

and we sometimes and unpredictably see an inversion of the chosen segment or segments on other backplanes seem to be changed.

Unfortunately the chip does not allow us to read back the register contents which would be a great help.

We have successfully completed a similar product using the MC9S08LL64CLH without the same problem.

We are suspecting a possible timing problem but any help would be appreciated!

[clivebuxton]

Hi

Thanks Tom, we have made some improvements but are still having difficulty with it. I'll update the thread when we find a full solution.

Cheers Clive

[TomE]

One thing to watch is the big/little endian problem. The Coldfire is big-endian. The HCS08 is also big-endian, but that looks to mainly be up to the compiler. The HCS08 only has an 8 bit accumulator. You might be extracting bytes out of 16 or 32-bit variables and assume they're in the same place they are on a PC.

Tom

[clivebuxton]

Freescale kindly sent this today, not checked it out yet.

I believe that the application note AN3796 can help you.

http://www.nxp.com/files/microcontrollers/doc/app_note/AN3796.pdf

also you can download the AN3796SW, on it you can find a sample code with the LCD driver.

http://www.nxp.com/files/microcontrollers/doc/app_note/AN3796SW.zip

[TomE]

I've had a quick look through the App Note and the Software package, and they look very good. They even come with spreadsheets to help with various parts of setting up an LCD.

The App Note says that the "non write cycle" is only required for the MCF51EM implementation, but doesn't say how to obey that requirement.

The software package explained this for me as it has this definition of a macro that is used between sequential writes:

#define _NonWrite  asm ( nop; )

So that seems to delay the CPU enough (and flushes the pipeline) so the CPU can obey the timing restrictions of the LCD controller.

Tom

[TomE]

Are you obeying both Cautions in the manual? That every write access is a byte-write and there must be a "non-write cycle" between consecutive writes? The Coldfire core may be faster than your MC9S08 implementation and so it may have timing problems the other one didn't.

I don't know what "non write cycle" means. Does it mean a CPU instruction cycle, a CPU memory cycle or a cycle on the slow peripheral bus the LCD controller is connected to? It may mean you have to execute a Coldfire "NOP" instruction (which isn't a NOP at all, check the CFPRM manual to see what the "real NOP" instruction is if you need it). It may mean you have to execute a dummy READ operation from an LCD register.

Tom

[clivebuxton]

Hi

Thanks for that, we saw the cautions mentioned in the reference manual and have taken them into account. We are all scratching our heads about this now so perhaps Freescale could advise?