Well spotted. This family of chips has clock gating to every peripheral, and all that can default to OFF on Reset and Power On.
Which is why it is worth sitting down and reading the manual from cover to cover before asking questions, or before starting coding. This feature of the chip is clearly detailed in multiple places, but you have to read everything to find those references. If the ports aren't working (the OP's problem ) you wouldn't think of reading the "Clock Gating" chapter to find the following:
5.2.5 Clock gating
The clock to each module can be individually gated on and off using the SIM's SCGCx
registers. These bits are cleared after any reset, which disables the clock to the
corresponding module to conserve power. Prior to initializing a module, set the
corresponding bit in SCGCx register to enable the clock. Before turning off the clock,
disable the module or place the module in its default configuration.
Turning off the clock for an enabled, working module can produce unexpected behavior.
There is no mention of this clock gating in the EGPIO chapter at all. it is a "Standard Module" that is used in multiple chips, and the "Clock Gating" is a feature of the chip provided in another module..
The OP said:
> I have studied the quick start demo that freescale provides, but
> it seems needlessly complicated for my purposes.
I would say NECESSARILY complicated. These are very complicated chips. If you want something you can get working easier, then start with a 6800, 2650, 68HC11 or Z80 from 30 years ago. :-)
But you really don't want to code these things from scratch. It may be satisfying to write all the code for a product "on the bare metal", but it sure isn't productive.
Tom