Having difficulties with the MCF5272 microprocessor QSPI module - Can't initiate a read cycle

[garrettschepper]

Hi, I am using the MCF5272 microprocessor QSPI module to interface with various on board ADC and DAC chips. My code is able to xmit out data over the Dout line to these devices, but is not able to receive any data in return on the Din line.

To simplify my debugging effort, I elected to focus on the AD7734 ADC only. I wrote a basic routine to read the AD7734 status register. I have placed it in a forever loop so that the QSPI signals can be monitored with a scope. From the scope I can see the write cycle signal activity on the QSPI Clk, chip selects, and Dout signals. These signals look correct. However, there is no follow on read cycle activity (eg. no activity on the Din line). I don’t know if this approach is correct, but I am causing a 2nd cycle by writing a 0xff to the AD7734. I would have thought that the QSPI would initiate a read cycle regardless. Why can’t I get a QSPI read cycle? What am I doing wrong here? Please help. Thank you in advance.

My code snippets are listed as follows:

int InitGpioPorts(void){    uint32 u32temp;    // Configure Port A to the defined signals, signals not defined are configured as GPIO pins.    *PortACntReg = SPI_CS3 | SPI_CS1 | USB_TP | USB_RP | USB_RN | USB_TN | USB_SUSP | USB_TXEN |USB_RXD;    *PortADirReg = CELLS_OFF_I | AUTOZERO_I | EXTSTRT_CELLS_I | FLASH_RDY_BSY_I | DOOR_AJAR_I;    // Configure Port B to all GPIO pins.    *PortBCntReg = ALL_PB;    *PortBDirReg = PSTAT_ADDR0_O | PSTAT_ADDR1_O | PSTAT_ADDR2_O | IDSHDN_O | ONE_WIRE_O                     | PSTAT_DETECT_A_I | PSTAT_DETECT_B_I | ANOUT1_DET_I | ANOUT2_DET_I;    // Configure Port D    u32temp = *PortDCntReg;    *PortDCntReg = (u32temp & 0xFFFFCFCF) | SPI_CS2 | PWM_1;    return (Channel::msOK);} // End InitGpioPorts()            // GJS: Test purposes stuff follows:            *SpiDelayReg = 0;       // set zero delay start and end for chip select enables            *SpiIRQReg = 0xF;       // IRQ will not be used clear any IRQs            i16temp = MASTER_MODE | TRANS_SIZE_8 | DATA_CAPT_FALL_EDGE | SET_BAUD_CTR;  // set baud rate to 1 MHz            *SpiModeReg = i16temp;            // FOREVER LOOP            while (1)            {                // Inverted chip select 14: PSTAT AD7734                 *SpiAddressReg = 0x00;          // QSPI WR BUF addr reg                *SpiDataReg = 0x44;             // Write to AD7734's comm reg, status reg addr to read it                *SpiDataReg = 0xff;             // To keep DOUT stable when reading.                *SpiAddressReg = 0x20;                      // QSPI CMD BUF addr reg                *SpiDataReg = INV_CS_DC_PSTAT_ADC_INPUT;           // Select DC_PSTAT_ADC_INPUT, 8 bits (QSPI_CS set to 0x01, inverted CS 14)                *SpiDataReg = INV_CS_DC_PSTAT_ADC_INPUT;           // Select DC_PSTAT_ADC_INPUT, 8 bits                // Start the QSPI process of xmitting the data...                *SpiIRQReg = CLEAR_TRANS_CMP_FLAG;                  // Clear complete bit             *SpiWrapReg = SPI_QUE_END_1 | SPI_QUE_START_0 | CHIP_SEL_ACTIVE_LOW;    // Set queue starting and ending points for the next data xfer.  No Wraparound.                *SpiDelayReg = QSPI_START_TRANSFER;                 // Start control transfer;                // Wait for the xfer to complete.                while (!(*SpiIRQReg & TRANS_CMP_FLAG));                *SpiIRQReg = CLEAR_TRANS_CMP_FLAG;                  // Clear complete bit                *SpiAddressReg = 0x10;          // QSPI RD BUF addr reg                i16temp = *SpiDataReg;          // Read the AD7734's status reg                i16temp = *SpiDataReg;          // Read the AD7734's status reg                tx_thread_sleep(50);        // GJS: For test purposes only,  delete when done.            } // end while(1)

[TomE · Accepted solution]

> However, there is no follow on read cycle activity (eg. no activity on the Din line).

> I am causing a 2nd cycle by writing a 0xff to the AD7734. I would

> have thought that the QSPI would initiate a read cycle regardless.

> Why can’t I get a QSPI read cycle?

I'm a little confused. All SPI cycles are simultaneously write and read. There are no SPI "read" or "write" cycle as such.

Whether the target chip (in your case the ADC) responds to the cycles as reads or writes depends on the data sent in the first cycle.

So are you seeing two cycles on the bus ("I am causing a 2nd cycle") or not ("there is no follow on read cycle activity")?

I suspect you are seeing two cycles, but that the Din signal isn't being driven on the second cycle like it should be if the chip was properly written with "0x44" on the first cycle.

You can get "out of step" with the ADC, so make sure it is being reset properly. Can you generate the "reset sequence" just in case?

Check the clock polarity against the diagrams in the ADC data sheet. Compare the clock edge and data edge timing in case you're using the wrong edges.

Check that the ADC is being clocked (its master clock input) and isn't held in Reset.

Pull Din high and low with a 100k resistor to make sure there are no shorts and that nothing else is driving it. I was going to suggest you program Din as a Gpio Input, but I see it is a dedicated pin on this CPU.

Compare your code with "14.5.8 Programming Example".

Tom

[garrettschepper]

Thank you for your reply Tom.  Sorry that I took so long to respond back.  We had an end of the year deadline to meet.

As it turns out, there were a few HW board issues that needed to be resolved first since they were new boards.  Once the issues were fixed, I was able to read from the AD7734 ADC without any problems. 

Thank you again,

-Garrett