FEC Differences

[PaulZ]

Hi,

Long time ColdFire 5307/5407 user, looking for comparison data on the various FEC modules (523x/527x/537x/548x/5445x).  From a driver perspective, how much different are these?  Is it possible or reasonable to write a common driver?

Thanks

[PaoloRenzo]

Yes it's possible, they share the same registers except for the 547x/548x which should work together with the DMA engine using microcode. Also I will check the 547x/548x errata just to understand all the implications. Besides that, it should be straight forward. Not considering obvious problems like registers with different names but you can solve that by using a common structure with all the FEC fields and just changing the base address.

Hope this helps

[PaulZ]

Thank you Paolo.  Just so I'm clear, the 547x/548x are different animals, all the rest (523x/527x/537x/5445x) are more-or-less the same?  Same register set and dedicated DMA engine?  Any other ColdFire variants that are different?

So, the 547x/548x came out first, then the FEC was redone for later chips?  Which was the first chip to use the new flavor of FEC?  Though I didn't mention the 5441x, I noticed that this chip doesn't refer to the "FEC".  Is this one completely different?

[PaoloRenzo · Accepted solution]

Don't know if the 547x/8x came first, I would think it came after the 523x and 527x family but not sure. The FEC handling is different because of the DMA microcode. The 5441x uses an enhanced FEC controller called ENET. However the ENET supports a legacy feature which makes almost backward compatible with the FEC. After that being said, except of the 547x/8x, all the FEC (and ENET in legacy mode) controllers are pretty much the same. You didn't ask but the same applies for Kinetis MCUs and Vybrid family. I would think the same applies to PPC FEC controller, but I never worked with that module in that architecture.

By using the legacy mode you will lose some cool features like protocol checksum in hardware, 16-byte auto alignment and IEEE1588.

Anyway, there are some small differences like endianess, or internal SRAM backdoor (small MCUs), GPIO handling, etc but are pretty much the same. The FEC IRQs are sometimes grouped in a single IRQ or splitted around in different vectors. That are the specific SoC instantiation of the module but I think you can get rid of them by layering your software.

Hope this helps