DMA Timer

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DMA Timer

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salman83
Contributor II

Hi,

I am using DMA timers. For some unknown reason, i am keep getting Transmit Frame Interrupt even this interrupt is disabled.

 

I am attaching the source code for the timer.

 

Regards.

Original Attachment has been moved to: timer.c.txt.zip

Original Attachment has been moved to: timer.h.txt.zip

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TomE
Specialist I

> > Is it a UART Transmit interrupt, an Ethernet Transmit interrupt, a QSPI Transmit interrupt a CAN Transmit interrupt or something else?

> Here is the list of interrupt controller #0 registers state when Transmit Frame Interrupt is called

You still haven't said which "Transmit Frame" interrupt, so I guess I have to try and ask the machine:

IPRH0  0x00200000  Bit 21, interrupt 53 - USB Interrupt

IPRL0  0x00780000  Bits 19, 20, 21, 22 - DMA Timer Interrupts

Is that the one you're getting? You didn't say you had USB Interrupts enabled and active.

Anyway, I can see obvious and serious problems with your interrupt controller programming.

You've made a common mistake. You've got the IDENTICAL programming for the ICRnx registers for the DMA Timers - all 0x25. Likewise for the Level Interrupts. Quoting from the chapter on the Interrupt Controller in the Reference Manual:

16.3.6 Interrupt Control Registers (ICRnx)

It is the responsibility of the software to program the ICRnx registers with unique and non-overlapping

level and priority definitions. Failure to program the ICRnx registers in this manner can result in undefined

behavior.

This happens a lot:

Re: MCF5235 Interrupt Vector 191

Re: Guidance on tracking down spurious interrupts

Re: Wrong interrupt handler being called after period of normal operation (MCF5235)

Re: CFV2 vector 125??? (vector or'ing?)

Re: Unhandled Interrupt vector 0x9f (159)

5223X Interrupt Controller -- setting levels/priorities

Re: Cpu_Interrupt while using Processor expert 52221DEMO

Re: Question about coldfire V2 interrupt priority

Re: Confusion on priority levels with exception handlers

Tom

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TomE
Specialist I

What CHIP are the DMA Timers in? Which CPU are you using?

Which peripheral is giving you the supposed "Transmit Frame Interrupt"? The DMA timers don't do this.

Is it a UART Transmit interrupt, an Ethernet Transmit interrupt, a QSPI Transmit interrupt a CAN Transmit interrupt or something else?

In case you've got that wrong you should provide the actual interrupt vector you're getting, so we can cross-check in case that's your mistake.

After you've written your question, you should read it as if you were someone else before posting it. Ask yourself if you've provided enough information for anyone ELSE to be able to understand what you're doing.

Tom

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salman83
Contributor II

Sorry about that. I should have written the whole info.

I am using MCF52259.

This is how initialized the supervisor register

// DMA Timer 0-1 : Read/Write (Supervisor/User mode)
MCF_SCM_PACR6 = 0x66;

// DMA Timer 2-3 : Read/Write (Supervisor/User mode)
MCF_SCM_PACR7 = 0x66;

This is how I enabled the interrupts

// Enable DMA Timer#0 interrupt
MCF_INTC0_IMRL &= ~MCF_INTC_IMRL_INT_MASK19;

// Enable DMA Timer#1 interrupt
MCF_INTC0_IMRL &= ~MCF_INTC_IMRL_INT_MASK20;

// Enable DMA Timer#2 interrupt
MCF_INTC0_IMRL &= ~MCF_INTC_IMRL_INT_MASK21;

// Enable DMA Timer#3 interrupt
MCF_INTC0_IMRL &= ~MCF_INTC_IMRL_INT_MASK22;

Here is the list of interrupt controller #0 registers state when Transmit Frame Interrupt is called

IPRH00x00200000
IPRL00x00780000
IMRH00xFFDFFFFF
IMRL00xFF87FFFE
INTFRCH00x00000000
INTFRCL00x00000000
IRLR00x10
IACKLPR00x45
ICR0010x08
ICR0020x10
ICR0030x18
ICR0040x20
ICR0050x28
ICR0060x30
ICR0070x38
ICR0080x00
ICR0090x00
ICR0100x00
ICR0110x00
ICR0120x00
ICR0130x00
ICR0140x00
ICR0150x00
ICR0160x00
ICR0170x00
ICR0180x00
ICR0190x25
ICR0200x25
ICR0210x25
ICR0220x25
ICR0230x00
ICR0240x00
ICR0250x00
ICR0260x00
ICR0270x00
ICR0280x00
ICR0290x00
ICR0300x00
ICR0310x00
ICR0320x00
ICR0330x00
ICR0340x00
ICR0350x00
ICR0360x00
ICR0370x00
ICR0380x00
ICR0390x00
ICR0400x00
ICR0410x00
ICR0420x00
ICR0430x00
ICR0440x00
ICR0450x00
ICR0460x00
ICR0470x00
ICR0480x00
ICR0490x00
ICR0500x00
ICR0510x00
ICR0520x00
ICR0530x24
ICR0540x00
ICR0550x00
ICR0560x00
ICR0570x00
ICR0580x00
ICR0590x00
ICR0600x00
ICR0610x00
ICR0620x00
ICR0630x00
SWIACK00x57
L1IACK00x18
L2IACK00x18
L3IACK00x18
L4IACK00x57
L5IACK00x18
L6IACK00x18
L7IACK00x18

Rest of the DMA Timer timer source code I already attached in my previous post.

Regards.

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TomE
Specialist I

> > Is it a UART Transmit interrupt, an Ethernet Transmit interrupt, a QSPI Transmit interrupt a CAN Transmit interrupt or something else?

> Here is the list of interrupt controller #0 registers state when Transmit Frame Interrupt is called

You still haven't said which "Transmit Frame" interrupt, so I guess I have to try and ask the machine:

IPRH0  0x00200000  Bit 21, interrupt 53 - USB Interrupt

IPRL0  0x00780000  Bits 19, 20, 21, 22 - DMA Timer Interrupts

Is that the one you're getting? You didn't say you had USB Interrupts enabled and active.

Anyway, I can see obvious and serious problems with your interrupt controller programming.

You've made a common mistake. You've got the IDENTICAL programming for the ICRnx registers for the DMA Timers - all 0x25. Likewise for the Level Interrupts. Quoting from the chapter on the Interrupt Controller in the Reference Manual:

16.3.6 Interrupt Control Registers (ICRnx)

It is the responsibility of the software to program the ICRnx registers with unique and non-overlapping

level and priority definitions. Failure to program the ICRnx registers in this manner can result in undefined

behavior.

This happens a lot:

Re: MCF5235 Interrupt Vector 191

Re: Guidance on tracking down spurious interrupts

Re: Wrong interrupt handler being called after period of normal operation (MCF5235)

Re: CFV2 vector 125??? (vector or'ing?)

Re: Unhandled Interrupt vector 0x9f (159)

5223X Interrupt Controller -- setting levels/priorities

Re: Cpu_Interrupt while using Processor expert 52221DEMO

Re: Question about coldfire V2 interrupt priority

Re: Confusion on priority levels with exception handlers

Tom

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