Coldfire V1, SCI Rx interrupt not triggering

[gordo]

Hello.

Can someone please tell me how to enable the rx interrupt for SCI1??

I have the RE and RIE bits enabled and if I poll the RDRF flag, I rx OK, but the ISR is not triggering!

I've looked at the .s32 and MAP files and see that the address of the ISR is correctly programmed at Vector 82 for the SCI1 rx interrupt.  When I set a break-point in the ISR it does not trigger, which leads me to believe that the interrupt hardware is not working correctly.

Is there a GIE bit (like microchip has) or something that I'm missing?

I'm using CodeWarrior v11.1 with the Universal Multilink FX.

Thanks for any help you can provide!

[TomE]

The CPU has an "Interrupt Priority Mask" field in the System Byte of the Status Register. That is the "master interrupt enable" on this CPU, corresponding to the single-bit interrupt enable/disable on other processors. This field allows the CPU to mask off (ignore) interrupt levels 1 to 6. The CPU comes out of reset with this set to "7", so all interrupts are masked OFF. After your code has all the hardware, memory, stacks and interrupts set up, the last thing it should do is to change this to "0" to enable interrupts.

I suggest you read the "CFPRM.pdf" Programmer's Manual, and also read through the CPU Core chapter for the CPU you're working with. Don't assume this CPU is "like a Microchip PIC". It is a lot more complicated than that, and those complications will trip you up.

Tom

[vicentegomez]

Please check the attached project

I hope this will help you