int rdWrIIc(uint8 *dataPtr, uint8 nBytes, uint8 slaveAddr, uint8 subAddr, uint8 rw){if(MCF_I2C_I2SR&MCF_I2C_I2SR_IBB) /* check if bus busy */{MCF_I2C_I2CR = 0; /* cf doc chap 22.6.1 */MCF_I2C_I2CR = MCF_I2C_I2CR_IEN + MCF_I2C_I2CR_MSTA;MCF_I2C_I2SR = 0; /* STOP condition */MCF_I2C_I2CR = 0;}MCF_I2C_I2CR = MCF_I2C_I2CR_IEN; /* enable IIC module */MCF_I2C_I2CR |= MCF_I2C_I2CR_IIEN; /* enable interrupt module IIC if ISR used */MCF_I2C_I2CR |= MCF_I2C_I2CR_MTX; /* send slave addess after START */MCF_I2C_I2CR |= MCF_I2C_I2CR_MSTA; /* master START condition */MCF_I2C_I2DR = slaveAddr; /* write slave address *//* here you have to wait for end of transfert *//* poll IIC ISR flag for example */MCF_I2C_I2DR = subAddr; /* write sub address *//* here you have to wait for end of transfert *//* poll IIC ISR flag for example */if(rw==IICWRITE) /* write device */{while(nBytes--) /* last byte — */{MCF_I2C_I2DR = *(dataPtr++); /* écriture de la donnée *//* here you have to wait for end of transfert *//* poll IIC ISR flag for example */}}else /*------------------------*/{ /* read device*/MCF_I2C_I2CR |= MCF_I2C_I2CR_RSTA; /* repeated START */MCF_I2C_I2DR = (uint8)(slaveAddr+1);/* Slave address + bit Read *//* here you have to wait for end of transfert *//* poll IIC ISR flag for example */if(nBytes 2) /* 1 byte ==> no ACK */MCF_I2C_I2CR |= MCF_I2C_I2CR_TXAK;MCF_I2C_I2CR &= ~MCF_I2C_I2CR_MTX; /* read mode */MCF_I2C_I2DR; /* dummy read to start */while(nBytes--) /* last byte – */{/* here you have to wait for end of transfert *//* poll IIC ISR flag for example */if(nBytes==1) /* if last but one */MCF_I2C_I2CR |= MCF_I2C_I2CR_TXAK; /* no ACK 4 last read */if(nBytes==0) /* if last byte */MCF_I2C_I2CR = 0; /* STOP condition */*(dataPtr++) = MCF_I2C_I2DR; /* read last */}}MCF_I2C_I2CR = 0; /* STOP condition */}
Message Edited by Alban on 2006-09-06 02:20 PM