I'm working on a custom board designed based upon LS1021ATWR board. In this modified board DDR3 DIMM modules are used whereas the LS1021ATWR uses DDR on-board chips.
I'm trying to modify the u-boot using QorIQ SDK ver 1.9 in order to support this modification. I'm comparing the u-boot code for ls1021atwr and ls1021aqds as a reference for my modifications.
I've used the CodeWarrior QCVS wizard and got the DIMM information by selecting "read from SPD" and it confirmed the read was successful and it generated the following files:
I understand that the .tcl file is used for initializing the DDR/controller from CodeWarrior for debug purpose.
The questions that I have are:
Hello Sina Sattari,
All these three files generated by QCVS contain DDR controller register values, you could use values in the section "# DDR Controller 1 Registers" in ddrCtrl_1.tcl.
In u-boot source, please modify DDR controller parameters in the section "Generic Timer Definitions" in the file include/configs/ls1021atwr.h according to the data generated by QCVS tool.
You could use the following yocto commands to rebuild u-boot.
$ bitbake u-boot -c cleansstate
$ bitbake u-boot -c patch
Go to the source folder "build_ls1021atwr/tmp/work/ls1021atwr-fsl-linux-gnueabi/u-boot-qoriq/2015.01+fslgit-r0/git" to modify u-boot source code.
$bitbake u-boot
Rebuild u-boot image.
Have a great day,
Yiping
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