T2080 : DDR Validation Error : D_INIT failed

[Arathi]

Hi NXP Support Team,

I am using T2080 processor with DDR Chip (MT41K512M16VRP-107 AAT:P)
Trying to execute DDR validation using code Warrior, it throws the below error : 

#################### Result for: write_read_compare_test ###### Run 1 #############################

Test was not executed!

Err. capture registers:
0xE20, 0x00000000 0xE24, 0x00000000 0xE28, 0x00000000 0xE40, 0x00000080
0xE44, 0x00000000 0xE48, 0x0000001D 0xE4C, 0x00000000 0xE50, 0x00000000
0xE54, 0x00000000 0xE58, 0x00010000

Dump:
0xF00, 0x00000000 0xF04, 0x00002100 0xF08, 0x0000000B 0xF0C, 0x14000C20
0xF10, 0x00000000 0xF14, 0x00000000 0xF18, 0x00000000 0xF1C, 0x00000000
0xF20, 0x00000000 0xF24, 0x10101010 0xF28, 0x10101010 0xF2C, 0x10101010
0xF30, 0x10101010 0xF34, 0x10103000 0xF38, 0x00000000 0xF3C, 0x00000000
0xF40, 0x00000000 0xF44, 0x00000000 0xF48, 0x08000001 0xF4C, 0x0A000000
0xF50, 0x08000C00 0xF54, 0x0C000C00 0xF58, 0x0C000C00 0xF5C, 0x0C000C00
0xF60, 0x0C000000 0xF64, 0x00000800 0xF68, 0x04444444 0xF6C, 0x44400000
0xF70, 0x00000000 0xF74, 0x00000000 0xF78, 0x00000000 0xF7C, 0x00000000
0xF80, 0x00000000 0xF84, 0x00000000 0xF88, 0x00000000 0xF8C, 0x00000000
0xF90, 0x00000000 0xF94, 0x00000000 0xF98, 0x00000000 0xF9C, 0x00000000
0xFA0, 0x00000000 0xFA4, 0x00000000 0xFA8, 0x00000000 0xFAC, 0x00000000
0xFB0, 0x00000000 0xFB4, 0x00000000 0xFB8, 0x00000000 0xFBC, 0x00000000
0xFC0, 0x00000000 0xFC4, 0x00000000 0xFC8, 0x00000000 0xFCC, 0x00000000
0xFD0, 0x00000000 0xFD4, 0x00000000 0xFD8, 0x00000000 0xFDC, 0x00000000
0xFE0, 0x00000000 0xFE4, 0x00000000 0xFE8, 0x00000000 0xFEC, 0x00000000
0xFF0, 0x00000000 0xFF4, 0x00000000 0xFF8, 0x00000000 0xFFC, 0x00000000

Data:
0x00000000

--------------------------------------------------------------------
Exception: (<<Error configuring the target! - DDR initialization failed: D_INIT was not cleared by hardware!>>)
--------------------------------------------------------------------
Target system was initialized 0 times and it took 0.000000 seconds.
Target system effective test execution took 0.000000 seconds.

We have tried changing DDR bus clock parameter in the properties tab with min value 303MHz and max value 933MHz still faces the same issue.

Please provide the support to resolve this

Thanks,
Arathi

[yipingwang]

DR_ERR_DETECT(0x00008E40) is read as 0x80, DDR_ERR_DETECT[ACE] is set.

For DDR_ERR_DETECT[ACE] can be set due to the following reasons:

1. The training sequence that the controller follows to calibrate the read data path was not able to complete. This would probably only happen if there was a hard failure on the memory interface caused by board-level issues or incorrect controller settings.
2. Incorrect termination of MDICx signals.
3. Write leveling calibration was not able to complete. This relates to improper settings of the DDR_WRLVL_CNTL register or board-level issues.

If there is SPD on your target board, please create a project with reading from SPD method.

If there is no DDR SPD on your custom board, please create a QCVS DDR project with default configuration, then modify Properties panel according to your DDR datasheet.

If your problem persists, would you please capture the CCS log to me to do more investigation?

When you use DDRv tool to connect to the target board, CodeWarrior connection Sever will be invoked automatically, please open it at the right bottom of the task bar, then type command "log v" in CCS console. In CodeWarrior IDE, please connect to the target board again, the low level communication log between DDRv and the target board will be captured in the CCS console.

[Arathi]

Hi @yipingwang ,

There is no DDR SPD on our custom board, so I have created a new QCVS DDR project with default configuration.

I have set the data rate to 1866 MT/s(DDR Bus clock is set to 933MHz) and have modified other properties panel parameters according to DDR datasheet.

Hereby attaching the CCS console log as requested by you.

Please do verify the log and let me know how to proceed further.

Thanks and Regards,
Arathi

[yipingwang]

Is this a new customer board bring up? or is this an existing board that DRAM is changed?

If board bring up, then check the DQ_MAP register, check the DRAM reset is aligned with HRESET.

[Arathi]

Hi @yipingwang ,

This is the new custom board bring up with T2080 Processor.

1.We are trying to configure and read DDR registers from initialization script file(init_sram.tcl)
But unable to find any DQ_MAP registers .

Can you please let me know where we can find the DQ_MAP register and how to check the same 

2.We are driving DDR_reset from the FPGA [Which controls out power and reset sequencing of the processor and device resets].

Thanks and Regards,
Arathi

[yipingwang]

I discussed this problem with the AE team.

My apologies. T2080 does not support DDR4 and does not have DQ_MAP registers.

for T2080, ask customer to put two signals (HRESET signal and DRAM reset signal) on the scope and trigger on rising edge of the HRESET. then zoom out till both falling rising edge of HRESET is on the screen. next make sure the DRAM reset signal assertion and de-assertion is aligned with the HRESET assertion and de-assertion.

[Arathi]

Hi @yipingwang ,

We have driven HRESET signal to DRAM reset signal, during this time HIGH reset was not getting asserted (Processor is in reset)

When both HRESET and DRAM reset signals were driven separately, the observation from the scope is provided below for your reference

In the below screenshot Green denotes DRAM RESET signal and yellow denotes HRESET signal.

Can you let me know why this HRESET is not getting asserted during this case

Is there any other possible way that we can try on this issue?

Thanks and Regards,
Arathi

[yipingwang]

I am discussing this problem with the AE team, please refer to the following to provide detailed information.

1. Schematics (the DDR section, or full schematics)
2. A register dump

Please open CCS console and type the following commands.

delete all

config cc cwtap

ccs::config_chain t2080

display ccs::read_mem 0 0x30000 0x8000 4 2 1024

ccs::write_mem 0 0x30000 0x8FB0 4 2 0x10000000

display ccs::read_mem 0 0x30000 0x8000 4 2 1024

3. The data rate customer wants to run on the this board
   
   Also the HRESET signal should NOT be directly connected to the DRAM reset signal since the voltages are different. the request is to make sure the DRAM reset signal and HRESET signal assert and de-assert together. it may not change or fix this issue but that is how HRESET and DRAM reset signals should behave.

[Arathi]

Hi @yipingwang ,

Please see the following information:

1.Attached DDR section schematics

2.CCS log 

3.Final Required Data rate = 1866MT/s
For Testing we are ok with low Data rate = 1600MT/s

In our case the DRAM reset signal and HRESET signal are not getting assert and de-assert together.

Thanks and Regards,
Arathi

[yipingwang]

Please dump DDR register values after running QCVS DDRv tool.

[Arathi]

Hi @yipingwang ,

Please see the below attached CCS log after running QCVS DDRv tool

Thanks,
Arathi

[yipingwang]

We are doing investigating, will provide more update later.

[yipingwang]

I got the following from the AE team.

Had a call with customer. at this point customer has a working DDR setting that is passing all the BIST test under the QCVS. customer saved the working/passing DDR settings. and will apply it to their SW  (bare metal or LSDK boot SW).

[Arathi]

Hi @yipingwang ,

As discussed, we have incorporated the generated results of BIST test under the QCVS into U-Boot and compiled them. Following is the output received on the terminal,

-----------------------

SPI boot...

Initializing....using SPD RD

WARNING: Calling __hwconfig without a buffer and before environment is ready

WARNING: Calling __hwconfig without a buffer and before environment is ready

WARNING: Calling __hwconfig without a buffer and before environment is ready

WARNING: Calling __hwconfig without a buffer and before environment is ready

Loading second stage boot loader .................................................................................................Bad trap at PC: 260021b0, SR: 0, vector=e00

**bleep**: 260021B0 XER: 00000000 LR: FFFD8B6C REGS: fffd7ed0 TRAP: 0e00 DAR: 00000000

MSR: 00000000 EE: 0 PR: 0 FP: 0 ME: 0 IR/DR: 00

GPR00: FFFE1BD4 FFFD7FC0 FFFC8000 002BFFFF 002BFFFE FFFCB140 FFFCB140 FFFCB130

GPR08: 00000000 00200000 00200000 FFFD7FC0 FFFE1460 00008170 00000001 000A4FB0

GPR16: 00400000 FFFC9001 00130114 FFFC8000 00800000 FFFA2FB0 00000000 260021B0

GPR24: 80400000 00000064 FFFE6164 00800000 00000000 00000000 FFFE6174 00102000

Call backtrace:

Exception in kernel pc 260021b0 signal 0

------------------------

Applied the DDR settings to U-Boot by disabling 'CONFIG_DDR_SPD' and adding DDR configurations in macros at '/include/configs/T208xRDB.h'.

Followed these steps to flash the SPL & U-Boot to board: https://docs.nxp.com/bundle/GUID-39A0A446-70E5-4ED7-A580-E7508B61A5F1/page/GUID-CF227019-184C-466E-A...

Attached are the DDR configurations & U-Boot config files for reference. Please let us know how we can proceed further.

Thanks and Regards,
Arathi

[yipingwang · Accepted solution]

In board/freescale/t208xrdb/ddr.c, there is no fixed DDR configuration code.

Please refer to board/freescale/p1010rdb/ddr.c, you need to define fixed_sdram function in board/freescale/t208xrdb/ddr.c to use the fixed DDR controller configuration parameters.

If your problem persists, would you please create a new thread to discuss more about u-boot porting.

[Arathi]

Hi @yipingwang ,

Defined fixed_sdram function as like p1010 RDB reference in board/freescale/t208xrdb/ddr.c.

Progressed the uboot debug and noted that DDR Initialization is happening as per QCVS tool values after adding fixed sdram configs but still uboot is not running completely. Below are the prints obtained

SPI boot... 

_fixed_sdram 

_fixed_sdram 

Configuring DDR for 1599.840 MT/s data rate 

Configuring DDR for 1599.840 MT/s data rate 

calling fsl_ddr_set_memctl_regs 

fsl_ddr_set_memctl_regs ddr3 

fsl_ddr_set_memctl_regs completed.. 

set_ddr_laws completed.. 

ddr_size: 0x40000000 

896.5 MiB left unmapped ddrreg 

DDR_DDR_SDRAM_CFG: 0xc7200008 

Loading second stage boot loader ................................................................................................. 

Copied 

running uboot 

Attaching the new thread link on u-boot porting for your reference.
https://community.nxp.com/t5/T-Series/T2080-Error-porting-u-boot-to-Flash/m-p/1752479#M4760

Thanks and Regards,
Arathi

[yipingwang]

Hello Arathi,

Thank you for your information.

Your new thread is taken by my colleague, she will continue to support you.

Thanks,

Yiping